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| ? eight-channel offline framer supports standard and frame hold-off frame alignment with crc-4 multiframe check, selectable out of frame criteria and change of frame alignment alarm, plus transparent non-framing mode frame alignment detection and loss of frame declaration comply with itu-t g.706 /ets 300 011 dual unipolar (hdb3/ami) or nrz line interface fractional e1; gapped clock or marker and aux. tx input clock, data, and frame pulse can be monitored for any e1 two-frame slip buffers in both receive and transmit directions with delay measurements supports time slot 16 ccs/cas signaling (cas debounced /processor-forced on a per time slot basis) detects and forces time slots 0 and 16 rai and ais; detects los, oof, oomf, oomf16, and aux pattern detects, counts and forces line code errors (bpvs and excess zeros), crc-4 errors, frame word errors, and crc errors (e-bits, 2 sa6 code counters) motorola/intel-compatible microprocessor interface auxiliary port with tsi for itu-t g.964/5 (v5.1/2) one-second interrupt input latches counter values and line events into shadow registers local, line remote, payload remote and time slot loopbacks with ansi t1.231 fractional t1 compatible loopback support per framer prbs/code word generator and analyzer for e1 and n x time slot testing four system interface options: transmission, data, mvip, and h-mvip/h.100 plus dual reference clock outputs ets 300 011, 300 233 and itu-t i.431 isdn support boundary scan capability (ieee 1149.1) single +3.3v power supply; 5 volt tolerant ttl inputs 208-lead or 256-lead plastic ball grid array package the e1fx8 is an eight-channel e1 (2048 kbit/s) framer designed with extended features for voice and data communications applications. ami and hdb3 line codes are supported with full alarm detection and generation per itu-t g.703, g.775 and i.431. integral receive dual unipolar rail dejitter buffers (itu-t g.735-739 and g.823) are provided. the transmit and receive sections of each of the eight framers are independent, including framing, with individual slip buffers to allow operation in a wide range of switching and transmission products. framing algorithm support for itu-t g.704, g.706 and ets 300 011 is included. access and control for signaling and data are provided via a motorola/intel-compatible microprocessor interface. for hdlc link applications, each framer supplies a full duplex hdlc controller with dual 128-byte fifos (for sa4-sa8 access) in addition to onboard latching of all performance parameters, requiring minimal software overhead. word-wide national bit read/write access is provided, with full sa6 code support. diagnostic, test, and maintenance functions are integrated, including e1 and per time slot local and remote loopback modes, per channel prbs/code word generator/analyzer and boundary scan (ieee 1149.1). sdh terminal or add/drop multiplexers supporting e1 byte- synchronous operation or e1 monitoring with g.706 annex c dcs, digital central office or remote digital terminals (exchange terminations and access nodes) e1 multiplexers e1 and fractional e1 csus atm products with integrated e1 interfaces lan routers with integrated e1 interfaces multichannel e1 test equipment internet access equipment with e1 and fractional e1 ports e1fx8 device 8-channel e1 framer TXC-03109 document number: preliminary TXC-03109-mb ed. 3, january 2001 e1fx8 TXC-03109 nrz data and signaling highways 8-channel e1 framer e1 dual rail / nrz data & clocks transceiver serial interface microprocessor interface system & fallback clocks ieee 1149.1 (jtag) interface system (terminal) side line side transceiver select 8 x 3 8 x 3 8 x 1 8 x 4 8 x 5 system i/o clocks 3 8 x 2 and controls 6 5 copyright ? 2001 transwitch corporation e1fx8 is a trademark of transwitch corporation transwitch and txc are registered trademarks of transwitch corporation mvip is a registered trademark of go-mvip, inc. data sheet preliminary preliminary information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications en g ineerin g for current information on this product. proprietary transwitch corporation information for use solely by its customers. applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers table of contents section page list of figures ............................................................................................................... .................... 3 overview ...................................................................................................................... ......................5 features ...................................................................................................................... .......................7 reference documents ........................................................................................................... ..........14 block diagram ................................................................................................................. ................15 block diagram description ..................................................................................................... .........16 lead diagram for 208-lead pbga package ...................................................................................22 lead diagram for 256-lead pbga package ...................................................................................23 lead descriptions .............................................................................................................. .............. 24 absolute maximum ratings and environmental limitations ........................................................... 42 thermal characteristics ....................................................................................................... ............42 power requirements ............................................................................................................. ...........42 input, output and input/output parameters..................................................................................... 43 timing characteristics ........................................................................................................ .............45 operation ..................................................................................................................... ....................79 line interface selection ...................................................................................................... ......79 receive dejitter buffer ....................................................................................................... .......81 line interface control ........................................................................................................ .......84 monitor mode .................................................................................................................. ..........85 system interface .............................................................................................................. .........86 transmission mode ............................................................................................................. .....87 data mode ..................................................................................................................... ...........93 mvip mode ..................................................................................................................... ..........97 h-mvip/h.100 mode ............................................................................................................. .100 framing ....................................................................................................................... ...........102 frame alignment ............................................................................................................... .....103 transmit framer ............................................................................................................... ......108 slip buffers .................................................................................................................. ...........115 delay ......................................................................................................................... .............118 signaling ..................................................................................................................... ............118 clocking and synchronization ................................................................................................12 4 ais generation and detection ................................................................................................12 6 auxiliary pattern generation and detection ...........................................................................126 hdlc channel .................................................................................................................. .....126 global microprocessor controls and alarms ..........................................................................130 maintenance ................................................................................................................... ........133 prbs generator and analyzer ...............................................................................................139 e1 tandem framing monitoring function ..............................................................................145 auxiliary port ................................................................................................................ ..........145 boundary scan ................................................................................................................. ......147 reset procedure ............................................................................................................... ......158 memory map .................................................................................................................... ..............159 common registers .............................................................................................................. ...159 per channel control and status indication registers ............................................................165 spare and reserved registers ..............................................................................................176 - 3 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers table of contents (continued) section page memory map descriptions ....................................................................................................... ......179 common registers .............................................................................................................. ...179 per channel registers ......................................................................................................... ..195 application diagrams........................................................................................................... .......... 272 package information ........................................................................................................... ...........273 ordering information........................................................................................................... ........... 275 related products ............................................................................................................... ............ 275 standards documentation sources ............................................................................................... 277 list of data sheet changes .................................................................................................... .......279 documentation update registration form* .............................................................................. 283 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1. e1fx8 TXC-03109 block diagram ........................................................................................ 15 2. e1fx8 TXC-03109 lead diagram for the 208-lead pbga package ..................................... 22 3. e1fx8 TXC-03109 lead diagram for the 256-lead pbga package ..................................... 23 4. dual unipolar (rail) receive interface timing..................................................................... 45 5. dual unipolar (rail) transmit interface timing.................................................................... 46 6. nrz receive interface timing (external transceiver) .......................................................... 47 7. nrz transmit interface timing (external transceiver) ......................................................... 48 8. nrz receive interface timing (fast sync mode) ................................................................. 49 9. nrz transmit interface timing (fast sync mode) ............................................................... 50 10. serial port write timing.................................................................................................... ..... 51 11. serial port read timing ..................................................................................................... ... 52 12. monitor mode timing......................................................................................................... .... 53 13. receive highway timing - transmission mode (recovered receive line clock) ................ 54 14. receive highway timing - transmission mode (system clock) ........................................... 55 15. transmit highway timing - transmission mode ................................................................... 56 16. receive highway timing - data mode (recovered receive line clock).............................. 57 17. receive highway timing - data mode (system clock) ......................................................... 58 18. transmit highway timing - data mode ................................................................................. 59 19. receive highway timing - mvip mode ................................................................................. 60 20. transmit highway timing - mvip mode ................................................................................ 61 21. receive highway timing - fractional e1 gapped clock (rec. line clock transmission & data modes) ..................................................................... 62 22. receive highway timing - fractional e1 gapped clock (system clock transmission & data modes) ........................................................................ 63 23. transmit highway timing - fractional e1 gapped clock (transmission & data modes) ..... 64 24. receive highway timing - 8 mbit/s h-mvip/ h.100 mode .................................................... 65 25. transmit highway timing - 8 mbit/s h-mvip/ h.100 mode ................................................... 66 - 4 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers list of figures (continued) figure page 26. shadow register timing ...................................................................................................... . 67 27. dpll reference input/output timing ................................................................................... 67 28. boundary scan timing ........................................................................................................ .. 68 29. intel microprocessor read cycle timing ............................................................................... 69 30. intel microprocessor write cycle timing ............................................................................... 70 31. motorola microprocessor read cycle timing........................................................................ 71 32. motorola microprocessor write cycle timing ........................................................................ 72 33. clock reference timing ...................................................................................................... .. 74 34. auxiliary port receive timing (clock slave) ......................................................................... 75 35. auxiliary port receive timing (clock master) ....................................................................... 76 36. auxiliary port transmit timing (clock slave) ........................................................................ 77 37. auxiliary port transmit timing (clock master) ...................................................................... 78 38. line interface for dual unipolar mode.................................................................................. 79 39. line interface for nrz mode ................................................................................................ 81 40. e1fx8 jitter transfer characteristics .................................................................................... 83 41. transceiver serial i/o timing ............................................................................................... . 84 42. transmit highway - transmission mode ............................................................................... 89 43. receive highway - transmission mode ................................................................................ 92 44. transmit highway - data mode ............................................................................................. 94 45. receive highway - data mode .............................................................................................. 96 46. transmit highway - mvip mode ............................................................................................ 98 47. receive highway - mvip mode............................................................................................. 99 48. transmit data and signaling highways - 8 mbit/s h-mvip/h.100 modes ........................... 100 49. receive data and signaling highways - 8 mbit/s h-mvip/h.100 modes ............................ 101 50. transmit slip buffer ........................................................................................................ ..... 116 51. receive slip buffer ......................................................................................................... ..... 117 52. receive signaling buffer .................................................................................................... . 121 53. transmit signaling buffer ................................................................................................... . 122 54. hdlc format ................................................................................................................. ..... 126 55. shadow register operation ................................................................................................ 13 2 56. local loopback .............................................................................................................. ..... 133 57. remote line loopback........................................................................................................ 134 58. bi-directional loopback..................................................................................................... .. 134 59. time slot remote and payload loopbacks ........................................................................ 135 60. time slot local loopback ................................................................................................... 136 61. ds0 remote loopback code sequence generator ............................................................. 136 62. prbs/ code word generator/ analyzer options with loopbacks ...................................... 142 63. tandem frame monitoring with national bit insertion......................................................... 145 64. auxiliary port connections .................................................................................................. 146 65. boundary scan schematic .................................................................................................. 14 8 66. typical applications using the e1fx8.................................................................................. 272 67. e1fx8 TXC-03109 208-lead plastic ball grid array package diagram ............................. 273 68. e1fx8 TXC-03109 256-lead plastic ball grid array package diagram ............................. 274 - 5 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers overview the e1fx8 provides the features of two qe1f- plus devices complemented by independent per time slot local or remote loopbacks, a gapped clock/marker system interface option, a per-channel prbs/code word generator analyzer, a per-channel time slot inband loopback activate/deactivate detector/generator (compatible with the t1fx8 and ansi t1.231), an internal selection option for the one-second clock, and frame pulse monitoring added to the e1 monitor function. the receive line interfaces are enhanced with dejitter buffers for loop timed applications and direct multiplexer interface applications. in addition, an intact mode for slip buffering unframed e1s, an auxiliary input for fractional e1 and ccs or isdn d channel access, and independent transmit or receive framing have been incorporated. for multichannel isdn or v5.1/v5.2 applications an auxiliary e1 rate port is provided that can directly connect to a multichannel hdlc controller for access to any user time slots from any of the channels for a maximum of 32 total. signaling debounce and a signaling change of state interrupt are incorporated along with certain alarms mapped to and from time slot 16 cas codes to automatically support itu-t g.732 alarm propagation. the hdlc fifos have been expanded to 128 bytes for each transmit and receive channel as well as being able to support back-to-back frames. a delay value register was added to the slip buffers and digital a-law or mu-law digital milliwatt or a programmable idle code is available per time slot. the system interface options are the same as those of the t1fx8 with both separate signaling, alternate data bit and full data inversion capability. the e1fx8 is available in the same 208-lead and 256-lead plastic ball grid array packages as the t1fx8. the e1fx8 packages have the same power, ground and signal lead configurations as the corresponding t1fx8 packages, except that some leads which are no-connect spares on the t1fx8 are used for additional power, ground and signal functions on the e1fx8. reduced power consumption is an added benefit of the e1fx8, which is powered from a 3.3 volt supply, but is still tolerant of inputs from 5 volt parts. the e1fx8 supports multiple applications, including sdh/pdh networks and data applications where multiple framing functions are required in a single board. the e1fx8 contains many features which allow it to be used in sdh add/drop multiplexers, e1 multiplexers, e1 and fractional e1 csus, pbxs, atm products, lan routers with integrated e1 interfaces, e1 internet access equipment, primary rate isdn interfaces, multichannel e1 test equipment, repeaters, access nodes and switches. in addition, the e1fx8 includes many advanced diagnostic, test, and maintenance features, including boundary scan (ieee 1149.1) and both e1 and time slot level loopbacks. the e1fx8 is well suited for embedded csu/dsu functions in routers and bridges and for test instruments needing a high degree of data manipulation. the e1fx8 supports ts0/crc-4 and ts16/signaling multiframes operating in an offine mode. either common channel signaling (ccs) or channel associated signaling (cas) is supported. the transmit and receive sections of each of the eight framers are independent, with individual slip buffers and independent framed or unframed operation to allow use in a wide range of switching and transmission products. each framer supplies a full duplex hdlc message controller with onboard transmit and receive fifos, and ts0 national bit access, in addition to onboard latching of all required performance parameters, requiring minimal software overhead and microprocessor bandwidth to support hdlc protocols. the hdlc controller is enhanced to include deep fifos (128 bytes each way) and a back-to-back capability where a single flag can separate frames. when not used for hdlc functions, the national bits are accessible to transmit and receive code words, with full sa6 bit functionality supporting ets 300 233 for isdn applications. the e1 digital line interface port is extremely flexible, allowing the device to connect to any industry standard line interface device with no external glue logic. ami, hdb3, and nrz line codes are supported with full alarm detection and generation. an optional 64-bit dual rail dejitter buffer meeting itu-t g.823 for jitter tolerance, g.735 and g.736 for jitter generation, and g.735/6/8/9 for jitter transfer is provided. optional frame pulse or drive bit output is available in the nrz mode. the nrz mode allows the e1fx8 to count externally detected code violations or to incorporate an external loss of clock/signal detector. the interface contains a serial port, which can directly control the external line interface unit and other components using the industry standard 'host' mode for device control. - 6 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the framer provides a microprocessor interface that is compatible with either motorola or intel processors. it is designed to act as an 8-bit peripheral using asynchronous bus transfers. polling or interrupt support and latching of critical events are provided to accelerate interrupt processing and reduce the burden on the attached microprocessor. individual alarm masks are available to ignore certain alarms or to operate different channels in different modes. direct access to the slip buffers is provided for time slots and the signaling rams, which makes sending special signaling or time slot codes possible with low overhead. scanning for signaling is facilitated with signaling debounce and interrupt on signaling change of state. the framer supports a wide variety of individual and multiplexed system interface options to permit seamless interfacing to many types of time slot-based devices. both mvip and hmvip/h.100 interfaces are provided for operation with many different system buses and devices. for maintenance support the e1fx8 incorporates a per e1 prbs code word generator/analyzer that provides 2 11 -1, 2 15 -1, qrss (2 20 -1) and 2 23 -1 codes in addition to a programmable 32-bit code word. in addition, a per e1 time slot loopback activate and deactivate function compatible with the t1fx8 and ansi t1.403-1998 fractional t1 loopback are provided. error forcing and diagnostic access are also provided. to support monitoring functions, the e1fx8 provides a bypass mode in which a received e1 signal is monitored and looped back to the transmitter. in this mode the sa4 through sa8 bits may be individually replaced and the crc-4 is updated to reflect only the changed bits, retaining end to end performance monitoring per itu-t g.706 annex c. although many advanced features are included, the device is optimized for the multichannel application. system i/o is minimized, and peripheral functions requiring significant logic or i/o have been reduced or eliminated. this device is well suited to systems requiring many e1 interfaces where real estate is at a premium. - 7 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers features the following features are supported by the e1fx8: framing modes and options offline framer (data passes uninterrupted from line to system even in loss of frame) follows itu-t g.706 (?88 or ?91) frame alignment detection and loss of alignment declaration thirty-two 64 kbit/s time slots basic frame structure ts0/crc-4 multiframe - two fas selectable algorithms (standard and frame hold-off; g.704/g.706) - crc-4 generation/check - crc-4 and non crc-4 multiframing automatic interworking(g.706 and tbr 04 versions) - reframe on excessive crc errors (>914 per second) ts16/signaling multiframe synchronization and alarm - two mas selectable algorithms (standard and enhanced) programmable out of frame control - 3 or 4 fas in error, 3 fas/3 nfas, or - 4 fas/4 nfas in error programmable frame synchronization - transparent, crc-4 disabled, crc-4 enabled, crc-4 enabled with e-bit alarms - microprocessor resync option full ets 300 011 compliant automatic alarm generation full ets 300 233 compliant national bit support independent transmit and receive transparent modes automatic crc-4/non crc-4 interworking per itu-t g.706-1991 appendix b or optionally per tbr-4 itaab note: 075 itu-t g.706 annex c compliant special loopback mode with update capabilities for national bits sa4-sa8 line codes and options nrz (unipolar) rail (hdb3 or ami line codes) - los detector with programmable recovery interval and ones density threshold covering itu-t g.775 and i.431 plus ets 300 233 - 16-bit bpv counters - wandel and goltermann or ttc t-berd bpv options plus an excessive zeros option nrz (unipolar) option - external bpv or los (sense option) using rnegn lead or - fast sync on receive (2 ms) option on rnegn lead - spare drive lead using tnegn lead or - transmit framing pulse option, 2 ms or 125 s using tnegn lead - clock polarity clock in/out selection - nrz data inversion option force transmit leads to 0, 1, or 3-state - 8 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers signaling methods supported common channel signaling (ccs) - time slot 16 - marker/gapped clock option with auxiliary input for external hdlc channel associated signaling (cas) in time slot 16 - with inversion option of transmit or receive - 0000 substitution option to prevent mimics of ts16 multiframe pattern cept irsm signaling - cas with e signal bit in sa4-sa8 bytes - available on signaling highway in transmission mode only signaling access and processing options dedicated signaling bus data stream embedded (time slot 16) directly addressable internal registers (microprocessor interface) per time slot individual signaling freeze option - with microprocessor rewrite capability for trunk conditioning - receive and transmit independent control e1 signaling freeze on los, lo16mf, oof and line ais signaling debounce option (programmable number of multiframes) signaling change of state interrupt and activity register indication four system interface options separate transmit and receive paths for both data and signaling for all four modes per device programmable sync start position for transmit (1 of 256) and receive (different 1 of 256) separate signaling bit inversion and data (time slot) inversion 2048 kbit/s transmission - 2 ms multiframe rate - defined signaling highway format; signaling for pair of time slots per frame plus alarms (ais and rai), national bits (sa4-sa8) and international bits (si) - receive system frame and clock are outputs when slip buffers bypassed - receive system frame and clock are inputs when slip buffers enabled - gapped clock/marker option with auxiliary input for fractional e1 and isdn support 2048 kbit/s data - 125 s frame rate - all abcd signaling bits available per time slot every frame - 32 time slots - receive system frame and clock are outputs when slip buffers bypassed - receive system frame and clock are inputs when slip buffers enabled - gapped clock/marker option with auxiliary input for fractional e1 and isdn support 2048 kbit/s mvip - 125 s frame rate - all abcd signaling bits available per time slot every frame - 32 time slots - receive system frame and clock are inputs; slip buffers always enabled 8 mbit/s h-mvip/h.100 - four e1 mvip formats byte-interleaved with 128 time slots - 125 s frame rate - receive system frame and clock are inputs; slip buffers always enabled - h.100 compliant timing - 9 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit and receive slip buffers system transmission and data interfaces full frame (30 or 31 time slots depending on cas or ccs operation plus time slot 0 fas and nfas storage) bypass option framed slips with time slots 0 through 31 repeated or skipped as a block e1 intact mode (slip buffering of an unframed e1 for all 32 time slots) mvip and h-mvip interfaces - slip buffers always enabled - 31 time slots features and options - current delay (0.5 s resolution) plus read and write pointer registers - microprocessor toggle option - e1 freeze option for microprocessor write option to individual time slots - time slot 0 freeze option with microprocessor rewrite capability - slip buffer status with common interrupt on slip of transmit or receive buffer receive dejitter buffers 64-bit dual rail or single rail with bypass option meets itu-t g.823 jitter tolerance, g.735/6 for jitter generation, and g.735/6/8/9 for jitter transfer and attenuation operates from a standard 2048 kbit/s backplane reference oscillator or 64512 khz reference fractional e1 support programmable receive gapped clock or enable pulse output per framer per time slot programmable transmit gapped clock or enable pulse output per framer per time slot fractional e1 data channel auxiliary input that multiplexes data into frame microprocessor interface directly addressable control and status registers all interrupts are maskable motorola split address/data intel split address/data global alarm indications - with separate channel activity pointers for line events, time slot 16 events and hdlc events global interrupt mask bits interrupt on alarms - positive transition - negative transition - both transitions hardware interrupt polarity selection hardware and software resets external line interface unit port serial port for the control of external line interface components using ?host? mode individual chip select and interrupt signals for each transceiver integration of line interface unit alarms microprocessor registers for read/write of line interface components broadcast capability to initialize all line interface components - 10 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers maintenance functions loopbacks - local with ais to transmit line option - line remote (all time slots) - payload remote (time slots 1 to 31) - per time slot (single or multiple) remote (from receive line to transmit line) - per time slot (single or multiple) local (from system interface to system interface) pattern generation/detection per e1 - prbs/code word generator/analyzer: 2 11 -1, 2 15 - 1, qrss (2 20 -1), 2 23 -1 pseudo-random patterns or 32-bit code word - full e1 framed or unframed (prbs only) - two insertion options: input to receive slip buffer or in place of transmit slip buffer input - two monitoring options: at line decoder output or at transmit slip buffer input - a-law or mu-law digital milliwatt in place of data for any time slot - programmable idle code insertion in place of data for any time slot - force programmable code in any time slot via slip buffer access - monitor for codes via read of the slip buffer ram or code word analyzer error and alarm insertion capability -bpv - crc-4 -fas/nfas -los -ais -auxp data link access - full duplex onboard hdlc message controller supporting back-to-back frames - 8-bit access via microprocessor interface - transmit from hdlc controller or system side (trans. mode; bypass national bits) - fifo status bits - zero stuffing/destuffing - flag detection/generation, abort message detection/crc-16 - 4 kbit/s to 20 kbit/s data link using any combination of the ts0 national spare bits - a 128-byte message buffer per transmit and receive directions per e1 e1 monitor access for multiplexed applications - select any e1 transmit or receive direction - receive line side - receive terminal side with frame pulse output - transmit side with frame pulse output - clock, nrz data and frame pulse brought to tristate leads for multiple e1fx8s on a bus per national bit byte code read and write synchronized to a multiframe time slot loopback activate/deactivate generation/detection per e1 - prbs generator/analyzer (2 7 - 1, 2 7 -1 inverted) pseudorandom patterns - any group of time slots - compatible with t1fx8 and ansi t1.231/ t1.403 ieee 1149.1 boundary scan high impedance on all leads for board testing sdh byte-synchronous mapper support - direct interface - rai and ais support to and from signaling highway - ts ais generation to transmit line ts16 (all channels) on sdh alarms - ts ais generation to signaling highway (all channels) on e1 alarms - ts rai generation to signaling highway (all channels) on e1 rai alarm - 11 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers alarm indications full ets 300 011 compliant automatic alarm generation programmable alarm generation and consequent actions los, loss of signal with programmable detect and recovery periods (itu-t g.775 and i.431) oof, out of frame losmf, loss of signaling multiframe (time slot 16) lcrcmf, loss of crc multiframe (time slot 0) rai, remote frame alarm mfrai, remote multiframe alarm (time slot 16) line ais, all ones received, selectable thresholds to meet itu-t g.775 or i.431 ts16 ais detection cofa, change of frame alignment signal multiframe error slip alarm for transmit or receive slip event line code violation counter with excessive zeros option far end block error (e-bit) counter far end block error for isdn te (sa6 code 0010) counter far end block error for isdn t interface (sa6 code 0001) counter sa6 code detectors for isdn auxiliary pattern detector (continuous 01 pattern on line) for isdn applications frame alignment word error counter crc-4 multiframe error counter prbs/code word error counter performance and fault monitoring los, line ais, ts16 ais, oof, losmf, lcrcmf, cfa, auxp, tx slip, rx slip, signaling change, mfrai, and rai are latched and shadowed (ts16 alarms optionally included with ts0 alarms) one-second update via selected line clock, one-second clock input, or 2048 khz backplane clock any change is recorded in a performance shadow register every second any fault that persists uninterrupted is recorded in a fault shadow register every second error counter roll-over generates a maskable processor interrupt one-second input will latch counter values into shadow registers - 12 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers auxiliary port full duplex 2048 kbit/s port timed from backplane oscillator, synchronization selections or an input any time slot (1 - 31) from any of the 8 channels (system or line side) may be assigned to any of the 32 output slots any time slot (1 - 31) of any of the 8 channels (system or line side) may be assigned from any of the 32 input slots supports v5.1 or isdn pri or bri via the transwitch mchdlc device clocks flexible receive and transmit clock selection - system clock - line clock before or after dejitter buffer - backplane reference clock two external clock inputs (2048 khz and optional 1 hz) 1 hz reference can be derived from either 2048 khz external clock or 1 of 8 line clocks before or after dejitter buffer and can be provided as an output dual reference outputs at 2048 khz or 8 khz - select any e1 framer for reference 1 (before or after dejitter buffer) - select any e1 framer for reference 2 (before or after dejitter buffer) - select 2048 khz or 8 khz (optionally synchronized to start of frame) power, package and environment 3.3 volt 5% single supply with 5.0 volt tolerant inputs power dissipation < 780 mw with all channels operational 17 x 17 mm 208-lead (1 mm ball pitch) pbga and 27 x 27 mm 256-lead (1.27mm ball pitch) pbga operating ambient air temperature range of -40 to +85 o c - 13 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers e1fx8 feature enhancements and differences versus the qe1f- plus twice the channel count of the qe1f- plus with more than the functionality of the qe1f- plus but: - less power than that of a single qe1f- plus by using 3.3v 0.35 micron technology - less board space than that of a single qe1f- plus by using pbga technology framing pulse monitor and selection of pre or post synchronizer monitor access deeper hdlc fifos (128-byte transmit and receive per e1 vs. 16-byte) and back-to-back messages loopbacks per time slot or group of time slots, both local and remote signaling debounce and signaling change of state interrupt one-second clock from one of eight receive lines or local oscillator with optional output prbs generator/analyzer per e1 for e1 or time slot(s) testing using 2 11 - 1, 2 15 - 1, qrss (2 20 -1), 2 23 -1 pseudorandom test patterns plus 32-bit code word fractional e1 support providing gapped clocks and enable pulses for assigned time slots (transmit and receive independent assignments) versus qe1f- plus gapped clock transmit and receive slip buffer delay value in registers for microprocessor wander control independent transmit and receive framing bypass with unframed slip buffering option byte-wide access for reception and transmission of each national bit plus code detectors and counters per ets 300 233 for sa6 independent data (time slot), alternate bit (even or odd) and signaling inversions isdn features (itu-t i.431 and ets 300 233) with los, ais, and national bit compliant operation plus auxp alarm auxiliary data input lead for fractional e1 or isdn d channel access programmable idle code, a-law or mu-law digital milliwatt per time slot sdh or itu-t g.732 alarm mapping to or from time slot 16 cas and time slot 0 alarms qe1f- plus pcm highway mode and 8 or 16 mbit/s transmission modes not supported rnegn is programmable for bpv counting, fast synch. or external los in nrz mode; qe1f- plus supplies a separate lintn lead for external los the frame pulse output option on the e1fx8 tnegn lead is programmable to 2.0 ms or 125 s; on the qe1f- plus it is only 2.0 ms separate latched, shadowed and activity registers for time slot 16 and miscellaneous events (excessive crc, one-second interrupt, signaling change of state, ts16 ais and out of signaling multiframe) separate auxiliary port for direct mchdlc access of 32 time slots for isdn and v5.1 ansi t1.231/ t1.403 compatible n x time slot loopback activate and deactivate generation and detection for compatibility with north american fractional t1 equipment bypass crc mode for monitoring and insertion of new national bits while maintaining performance e1fx8 feature differences versus the t1fx8 e1fx8 provides both per time slot remote and per time slot local loopbacks; t1fx8 only provides per time slot remote loopback. e1fx8 allows the slip buffer recentering to toggle; t1fx8 only recenters to least delay. e1fx8 allows the prbs generator or analyzer to be connected to either transmit or receive path; t1fx8 is fixed so the generator is on the transmit path and the analyzer is on the receive path. e1fx8 has an auxiliary port for direct mchdlc access of 32 time slots for isdn and v5.1. e1fx8 has per e1 receive dejitter buffers. e1fx8 permits an internally generated one-second clock to be an output; t1fx8 it is only an input. e1fx8 has no equivalent of automatic performance report message generation. e1fx8 has no equivalent of n x 56 kbit/s time slots. - 14 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers reference documents itu-t g.703 physical/electrical characteristics of hierarchical digital interfaces. 1993. itu-t g.704 synchronous frame structures used at primary and secondary hierarchical levels. 1988, 1991 and 1998. itu-t g.706 frame alignment and cyclic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704. 1988, 1991 and 1995. itu-t g.711 coding laws for pcm systems. 1988. itu-t g.732 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s. itu-t g.735 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 384 kbit/s and/or 64 kbit/s. itu-t g.736 characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s. itu-t g.738 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 320 kbit/s and/or 64 kbit/s. itu-t g.739 characteristics of an external access equipment operating at 2048 kbit/s and offering synchronous digital access at 320 kbit/s and/or 64 kbit/s. itu-t g.775 loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria. itu-t g.796 characteristics of a 64 kbit/s cross-connect equipment with 2048 kbit/s access ports. itu-t g.821 error performance of an international digital connection forming part of an integrated services digital network. itu-t g.823 the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 3/93. tu-t g.964 v-interfaces at the digital local exchange (le) - v5.1- interface (based on 2048 kbit/s) for the support of access network (an). 3/95. itu-t g.965 v-interfaces at the digital local exchange (le) - v5.2- interface (based on 2048 kbit/s) for the support of access network (an). 3/95 itu-t i.412 isdn user-network interfaces. multiplexing, rate adaption and support of existing interfaces. itu-t i.431 isdn user-network interfaces. primary rate user-network interface - layer 1 specification. 3/93 itu-t i.441 isdn user network interface data link layer specification. itu-t o.151 error performance measuring equipment operating at the primary rate and above. 10/92. itu-t o.152 error performance measuring equipment for 64 kbit/s paths. 10/92. itu-t o.162 equipment to perform in-service monitoring on 2048, 8448, 34 368, 139 264 kbit/s signals. itu-t q.516 operation and maintenance functions. prets 300 011-1, -2, -3 integrated services digital network (isdn); primary rate user network. interface (uni); part 1: layer 1 specification; part 2: conformance test specification for interface i a and i b ; part 3: implementation conformance statement.november 1996 draft. ets 300 233 plus amendment a1. integrated services digital network (isdn); access digital section for isdn primary rate. may 1994 with amendment of march 1995. ieee 1149.1 standard test access port and boundary-scan architecture, may 1990. mvip, h-mvip multi-vendor integration protocol. working document, april 1995. enterprise computer telephony forum, h.100 rev. 1.0 hardware compatibility spec. ct bus ansi t1.231 -1997 ansi t1.403-core and -rob; draft for letter ballot sept. 1998 tbr 4, november 1995 and amendment a1, dec. 1997. itaab (trac isdn type approval advisory board) advisory note number: 075 rev. 1 1998 - 15 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. e1fx8 TXC-03109 block diagram receive slip buffer transmit slip buffer receive framer transmit framer receive signaling transmit signaling hdlc transmit line interface receive line interface framer #1 11 11 11 7 7 7 prbs generator prbs analyzer receive transmit line side system (terminal) side rtdat1* rtclk1 rtfrm1 rtsig1*+ ttsig1*+ ttdat1* ttclk1 ttfrm1 scout1 scout2 moto d(7-0) a(12-0) sel wr /lds rd , rd/wr rdy/dtack int/irq line interface control bposc conf(0-1) sregt rpos1/rnrz1 rneg1/rscan1 rclk1 tpos1/tnrz1 tneg1/tdrv1 tclk1 lcs1 rposn/rnrzn rnegn/rscann rclkn tposn/tnrzn lsclk lsdo lsdi ieee 1149.1 scan i/o: tbck tbms tbdi tbdo trs highz test rtfrmn rtclkn rtdatn* rtsign*+ rtauxn+ reset sysci p i/o test access port framer #2 framer #3 framer #8 tnegn/tdrvn tclkn lcsn (n=2-8) framer (channel) blocks (8) * note: signaling and data for each group of four framers is multiplexed on framer 1 and 5 signaling and data leads for hmvip/ h.100 mode. interface ttaux1+ rtaux1+ ttaixn ttfrmn ttclkn ttauxn+ ttdatn* ttsign*+ time slot loopbacks & access local & remote clock selections ttaix1 (n = 2-8) monitor interface control monclk mondat monfrm . . . . . . . . . pwdn + note: for 208-lead pbga line interface control and monitor interface control share leads, and ttsign/rtsign share leads with ttauxn/rtauxn. + + loopbacks rtauxn can also be used to externally monitor prbs out of lock. dejitter buffer auxiliary interface raclk rasync radat taclk tasync tadat dpll osc 64512 khz to djbs dpllref - 16 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers block diagram description a simplified block diagram of the 8-channel e1 framer (e1fx8) is shown in figure 1. the e1fx8 consists of the following major blocks: eight framer blocks, line interface control, clock selections, microprocessor input/output interface, auxiliary interface, monitor interface control, dpll oscillator and test access port. line interface each of the eight identical framer blocks consists of the following sub-blocks: receive and transmit line inter- face blocks, receive and transmit framer blocks, hdlc block, receive and transmit slip buffer blocks, prbs generator, prbs analyzer, and receive and transmit signaling blocks. the receive and transmit line interface blocks connect each of the eight framers to an external line interface transceiver, which performs the liu and clock recovery functions. the interface to the external line interface transceiver can be configured for two interface modes: a dual unipolar (rail) interface or a nrz interface. when the dual unipolar interface mode is selected, input data from the external line interface transceiver is clocked into the e1fx8 on leads rposn and rnegn using the recovered receive clock present on the rclkn input lead (where n=1-8 identifies one of the eight framers). in the transmit direction, unipolar data is clocked out of the e1fx8 on leads tposn and tnegn by the transmit line clock present on the tclkn output lead. for reduced power dissipation in protection switching applications, the tclkn, tposn, and tnegn leads for the eight framers may be forced low, by per channel control bits as well as a power-down lead (pwdn ) which affects all eight framers. control bits are provided in the memory map which enable the unipolar data to be clocked in and out of the e1fx8 on either edge of the clocks. for the dual unipolar interface mode, the e1fx8 provides either a high density bipolar of order 3 (hdb3), or an alternate mark inversion (ami), coder and decoder function, and loss of signal detection. the loss of signal detector is programmable to meet the requirements specified in the itu-t recommendation g.775, i.431 or ets 300 233. a 16-bit performance counter is provided for each framer, for counting hdb3 or ami coding violation errors with an option to include excessive zeros (blocks of four contiguous zeros in hdb3 and blocks of sixteen contiguous zeros in ami). when the nrz interface mode is selected, nrz data is clocked in at the rnrzn lead by the recovered received clock present on the rclkn lead. the nrz data is clocked out of the e1fx8 on the tnrzn lead by the transmit clock present on the tclkn lead. control bits are provided in the memory map which enable the nrz data to be inverted in and out of the e1fx8 or to be clocked in and out of the e1fx8 on either edge of the clocks. in nrz interface mode, the hdb3 or ami coder and decoder functions are bypassed. however, bipolar violations which are detected in the external line interface transceiver may be clocked into the e1fx8 on the rnegn/rscann lead and counted in the associated 16-bit coding violation performance counter. the rnegn/rscann lead may be used to bring in external los indications in place of code violation counts or to force frame synchronization. in nrz mode the tnegn/tdrvn lead may be used to provide a fixed drive signal or it can output a 2 ms or 125 s frame sync pulse. the remote line loopback function for each framer is implemented in the line interface blocks. a 64-bit dejitter buffer is provided to remove line, demapping or demultiplexing jitter when an external dejitter buffer is not provided by a liu or other device and when receive slip buffer usage is not practical for a given application. both rposn/rnrzn and rnegn are dejittered using a digitally controlled oscillator and 64-bit fifo. the transfer function is that of a single pole low pass filter with the pole at 9 to 11 hz; wander is passed through but jitter is attenuated. remote loopbacks also go through the dejitter buffer and clock reference selec- tions are taken from the dejittered clock outputs when it is enabled. the onboard dpll runs at 64512 khz to operate the dejitter buffers. the signal may be output, or the dpll may be disabled and the dejitter buffers may be operated from an external clock via lead dpllref. - 17 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive framer the receive framer block for each framer performs two basic functions: frame synchronization and channel associated signaling (cas) multiframe alignment. the frame synchronization circuit has two framing options: frame synchronization based on the frame alignment signal (fas) carried in time slot 0, or frame synchroniza- tion based on the frame alignment signal and validation by the crc-4 multiframe alignment signal. the frame synchronizing circuit meets the framing requirements specified in itu-t recommendations g.704 and g.732 as well as ets 300 011 and tbr 4 with itaab note 75 supported optionally for automatic crc-4/non crc-4 interworking. the frame synchronization out of frame alarm criteria are programmable to use 3 or 4 framing words in error, with or without validation by the crc-4 multiframe alignment signal and with or without nfas. framing word errors and crc-4 errors are counted in performance counters. the receive framer block moni- tors and detects a remote alarm a-bit (bit 3) in time slot 0 as specified in itu-t recommendation g.704 and g.732, counts e-bit errors (which represent far end performance), and counts crc-4 errors (which represent near end performance). detectors for ais, the auxiliary pattern, and loss of multiframe alignment via excessive crc-4 errors are provided. a non-framing mode is enabled individually for the receive path when the e1fx8 is configured in the transmission or data modes. the non-framing mode bypasses the receive framer block, but the receive slip buffer may be included optionally to provide an intact mode, which slip buffers the entire e1 signal with a random start position. when frame alignment is acquired, the cas multiframe pattern in time slot 16 is detected for alignment. after multiframe alignment is established, the signaling bits are forwarded to the receive signaling block for buffer- ing, debouncing, microprocessor access, and formatting into the signaling highway data stream. per sa4-sa8 (national bits) byte-wide registers are provided to store the entire multiframe content of each individual sa4-sa8 bit stream. this implementation supports a wide variety of options like isdn access, cept irsm and itu-t g.704 synchronization status messages. in addition, sa6 is provided with code detectors and debounce circuitry plus 10-bit counters for two specific codes in support of ets 300 233 (isdn far end block errors). sa5 and sa7 codes are also supported. the e1fx8 complies with the g.706 itu-t recommendation, which specifies the frame alignment and crc procedures relating to basic frame structures defined in recommendation g.704. receive slip buffer each receive slip buffer controls time slot access and retiming for a framer by using a two-frame receive buffer that can be optionally bypassed in the 2 mbit/s transmission and data modes. the receive slip buffer is always enabled in mvip and hmvip/h.100 modes. when the receive slip buffer is enabled, received time slots are written into the buffer by recovered receive clock rclkn, and read out as data (rtdatn) from the slip buffer by the system input clock rtclkn. a phase shift between the two clocks is detected in this block and a deletion or repetition of one frame of data (32 time slots for intact mode, 31 time slots for ccs or isdn, or 30 time slots if time slot 16 is assigned for signaling) is provided when the buffer reaches an almost full or almost empty condition, respectively. microprocessor access is provided to the delay register indicating delay in 0.5 s increments (a measurement is made of delay in single bit increments) as well as the read and write pointers. channel 0 and channel 16 (when channel 16 is assigned for channel associated signaling) are not affected by a slip in the framed mode of operation. buffer alarm indications of slip repeat, slip skip and slip error are pro- vided. the slip buffer may be toggled by the microprocessor, or automatically recentered as described above. individual time slots are accessible by the microprocessor for the insertion of system idle or out of service codes. when the receive slip buffer is bypassed, the receive clock (rtclkn) and data (rtdatn) are provided as outputs, along with a receive sync signal (rtfrmn), all derived from rclkn or from bposc if an los con- dition is present. for maintenance purposes, a transmit time slot from the transmit slip buffer or data highway may selectively replace a time slot from the receive line interface. one bit per time slot is provided for this purpose in the microprocessor interface for time slots 0 through 31. - 18 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling for channel associated signaling (in time slot 16), a multiple 120-bit signaling buffer is used to store the sig- naling bits which have been extracted by the receive framer (one main buffer that contains the current or debounced abcd bits, a temporary buffer that contains the current and previous multiframe abcd bits used for debouncing, and a count buffer indicating the number of frames in a row that match). the signaling bits are stored sequentially in the signaling buffer in the order that they were received. the main signaling buffer may be read, frozen, and written to by the microprocessor. if signaling is to be disabled for a particular channel, the abcd signaling bits for that time slot are frozen in their present states and these frozen values are repeatedly sent to the system interface receive signaling highway (rtsign); since the microprocessor is able to over- write the frozen values, special signaling states may be substituted for received signaling. when a loss of sig- nal, line ais, loss of multiframe alignment, or an out of frame condition is detected, the signaling bits are automatically frozen in their present states. the signaling bit states are held and repeated to the receive sig- naling highway (rtsign) until framing has been recovered. when signaling debounce is provided, the main 120-bit buffer is used to store the debounced signaling bits; this buffer is updated if, in the current multiframe, the signaling bits received in time slot 16 match the signal- ing bits received in the previous multiframes (the number is programmable). the signaling bits are debounced as a nibble. the main signaling buffer, and hence the receive signaling highway (rtsign), are not updated unless the signaling bits match for n consecutive multiframes. if a change occurs, an optional interrupt is gen- erated to the microprocessor indicating a change of signaling state. for cross connect and itu-t g.732 applications, particular abcd codes can be used to indicate line rai or line ais. when line ais, loss of multiframe alignment, loss of signal, or out of frame occurs, a programmable abcd code can be sent to the system interface signaling highway, rtsign, in place of a frozen signaling code. for line rai (time slot 0 a-bit) or the multiframe alarm (y-bit in time slot 16) a different programmable abcd code can be sent to the system interface signaling highway (rtsign). system interface on the terminal side, the system interface interconnects the eight framers with the system. for each framer there is a separate receive and transmit highway for the 2 mbit/s transmission, data, and mvip interface modes of operation. the receive highway consists of a data bus (rtdatn), a signaling bus (rtsign), a clock (rtclkn), a gapped clock/enable signal (rtauxn), and a synchronization signal (rtfrmn). the transmit highway consists of a data bus (ttdatn), a signaling bus (ttsign), a clock (ttclkn), a gapped clock/enable signal (ttauxn), an auxiliary data bus (ttaixn), and a synchronization signal (ttfrmn). when rtfrmn is an input, and for ttfrmn, the frame start position is programmable independently for transmit or receive (all transmitters are programmed to one of 256 values and all receivers are programmed to either the same one of 256 values or a different value). transmit slip buffer a transmit slip buffer is provided to absorb low speed jitter in the transmit data. each transmit slip buffer block controls time slot access and retiming for the framer by using a two-frame buffer that can be optionally bypassed in the transmission and data modes. when the transmit buffer is enabled, transmit time slots are written into the buffer by the transmit system clock (ttclkn), and they are read out from the buffer by the receive clock (rclkn), local oscillator (bposc), or transmit system clock (ttclkn). a phase shift between the two clocks is detected in this block, and a deletion or repetition of one frame of data (i.e., 31 time slots, or 30 time slots if time slot 16 is assigned for signaling) is provided when the buffer reaches an almost full or almost empty condition, respectively. microprocessor access is provided to a delay register which indicates the delay through the slip buffer in increments of 0.5 s as well as the read and write pointers. buffer alarm indica- tions of slip repeat, slip skip and slip error are provided. the slip buffer may be recentered or toggled by the microprocessor, or automatically as described above. individual time slots can be accessed by the micropro- cessor for the insertion of system idle or out of service codes or for reading to detect special codes or test pat- terns. - 19 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit framer the transmit framer block forms the frame (with or without the crc multiframe) with time slots read from the transmit slip buffer block, or the data highway if the slip buffer is bypassed, and signaling information from the transmit signaling block. the international bits from the signaling highway are inserted into time slot 0 via a buffer when the framing mode is selected. the national bits in time slot 0 can be inserted from the hdlc block, from the system interface or via a byte-deep buffer per national bit position. the crc-4 is calculated as specified in itu-t recommendation g.704 and inserted in time slot 0. the remote alarm indication for time slot 0 is inserted as a result of a receiver loss of frame alignment alarm, or by the microprocessor, or via the signaling highway (ttsign); both g.706 and i.431 algorithms can be selected. the e-bits are updated to indi- cate the sub-multiframes received with bad crc-4. a single frame bit error, or crc-4 error, can be generated for test purposes. the transmit framer and transmit slip buffer can be bypassed if the unframed mode of operation is selected in the 2 mbit/s transmission mode. for maintenance purposes the transmit framer may selectively replace a time slot from the slip buffer or data highway with a time slot received by the e1fx8 receive line interface. one bit per time slot is provided for this purpose in the microprocessor interface for time slots 1 through 31; time slot 0 is not looped back. per sa4-sa8 (national bits) byte-wide registers are provided to transmit the entire multiframe content of each individual sa4-sa8 bit stream as a code. this is particularly useful in isdn applications. transmit signaling for channel associated signaling (in time slot 16), a 120-bit signaling buffer is used to store the signaling bits which have been input on the transmit signaling highway (ttsign). the signaling bits are stored sequentially in the signaling buffer in the order that they were received. the signaling buffer may be read, frozen, and writ- ten to by the microprocessor. if signaling is to be disabled for a particular channel, the abcd signaling bits for that time slot are frozen in their present states and repeatedly sent in channel 16. the microprocessor has the ability to write to the signaling buffer when signaling is disabled for the purpose of direct control of channel associated signaling for one or more time slots providing call control or trunk conditioning functions. fdl hdlc controller each framer has a full duplex hdlc block. the hdlc block is configurable to send and receive messages using any of the five spare bits reserved for national use (sa bits) in time slot 0 in alternating frames. a 128-byte fifo is provided in each direction. interrupt and status alarm support is provided to facilitate fifo servicing for long messages. the hdlc controller supports zero bit stuffing/destuffing, itu-t crc-16 genera- tion/checking, flag generation/detection, abort generation/detection, start of frame detection, end of frame detection, and fifo underflows and overflows. a separate message length register is provided in addition to a byte count register to permit the reception of back-to-back fdl messages. the fdl function may be bypassed. line interface control the line interface control block provides a serial port for communicating with an external line interface trans- ceiver that has the ?host mode? feature. this allows the system microprocessor to control the transceiver through the e1fx8 without any external glue logic. the interface consists of a data output lead (lsdo), clock output lead (lsclk), and a data input lead (lsdi). these signals are shared between all of the transceivers. each transceiver is selected by the e1fx8, using individual chip select output signals (lcsn ). address, received data, and transmit data registers are provided to read or write individual registers in each line inter- face transceiver as well as to provide a broadcast mode to ease redundancy or initialization. - 20 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers monitor interface control for system applications that do not have direct e1 line access (e.g., e123mux or qe1m devices), the monclk, mondat and monfrm leads can be configured to provide an e1 monitoring of any transmit or receive e1 line. these leads are tristateable to allow bussing of multiple e1fx8s. monitoring of the received side can take place prior to or after frame synchronization, with the latter supplying a signal on monfrm; the transmit side monitoring always supplies the frame synchronization signal monfrm. test access port the test access port block includes a five-lead test access port (tap) that conforms to the ieee 1149.1 stan- dard. this test access port block provides for external boundary scan to read and write the e1fx8 input and output leads from the tap for board and component testing. in addition, a four-byte read-only memory location is provided for reading the jedec manufacturer id, e1fx8 part number, and version number of the device as part of the microprocessor interface. maintenance: prbs generator and analyzer blocks, loopbacks to assist in testing, built-in pseudo-random binary sequence (prbs) generator and analyzer blocks are pro- vided on a per e1 basis, framed or unframed. the prbs generator and analyzer supports the 2 15 -1 bit pseudo-random binary sequence which is specified in the itu-t recommendation o.151. in addition to the o.151 a 2 20 -1 (qrss), 2 11 -1 (o.152), and a 2 23 -1 pseudo-random binary sequence are provided. an optional 32-bit code word may be substituted for the prbs in framed mode only. each e1 framer may select where the prbs generator and analyzer are connected so that both line testing (generator on the transmit side and analyzer on the receive side) and system testing (generator on the receive side and analyzer on the transmit side) can be supported. the output of the analyzer is provided in a per channel register as well as counted in a 16-bit out of lock counter. the prbs may operate in a framed or unframed mode for the entire e1 channel or it may operate over a single time slot or group of time slots to support fractional e1 and per time slot mainte- nance. the e1fx8 provides local loopback (transmit framer looped to receive framer), remote line loopback (receive line signal looped to transmit line), and payload loopback (time slots 1 through 31 from receive line looped back but with a locally generated time slot 0) options for each e1 channel. in addition, any one or more received time slot (except time slot 0) may be selected and looped back, and transmitted in place of the time slot input from the data highway, or any one of the transmit time slots may be substituted for a received time slot. the e1fx8 provides time slot loopback activate and deactivate code detection and generation in support of the ansi t1.231/t1.403-core standard, permitting single-ended transatlantic loopback testing of fractional t1s/e1s using the e1fx8. microprocessor interface the e1fx8 can be configured to operate with either intel- or motorola-compatible microprocessors via the microprocessor input/output interface block. interrupt capability is provided with global and individual framer mask bits. global event and polling registers are provided to indicate the type of alarms present and on which e1 channels these alarms or events are taking place. one-second error counters, performance monitors and fault monitors are supported by shadow registers. these shadow registers permit performance and fault statis- tics to be gathered on one-second intervals with minimal microprocessor overhead. an option is provided which permits the interrupt polarity to be inverted. an external system clock (sysci) of 19 to 25 mhz is used to run the internal state machines. this section of the design is the same as the t1fx8 except for the fact that the signaling activity register and the sa6 status register are read to clear registers. - 21 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers clock selections the e1fx8 provides a pair of reference clock outputs which are each selected from one of the eight rclkn inputs after the dejitter buffer, if it is enabled. if not selected, the output is tristated to allow multiple e1fx8s to share a single bus. if a selected channel experiences a los, the output is forced low. one-second perfor- mance monitoring can be triggered by an external 1 hz clock (sregt) as an input, or it can be triggered by counting the 2048 khz local oscillator (bposc) input or a selected received line clock (rclkn). when the one-second clock is derived internally, sregt is an output to synchronize additional e1fx8 and/or other devices; this is the only difference outside of divide ratios between the t1fx8 and the e1fx8. bposc is used to substitute for rclkn when the receive line clock is selected for the system side output and los occurs. auxiliary port interface for system applications that need to support isdn pri, isdn bri (multiplexed) or itu g.964/5 v5.1/2 functionality, an auxiliary port is provided with 32 transmit and 32 receive 64 kbit/s time slots, each individually programmable to any receive or any transmit time slot (1 to 31) to or from any of the eight e1 framer channels, either line or system side. no broadcast or concatenation functionality is provided as all applications are 64 kbit/s or subrates of 64 kbit/s. each connection is passed through a fifo function with independent depth control to account for line side or system side clock differences from the auxiliary port clock. thus buffering is provided by this block to match this block?s clock with the 16 transmit e1 and the 16 receive e1 line clock domains. for data output from this port on the radat lead, the clock and frame reference signals, raclk and rasync, may each be an input or an output which is either derived from the bposc lead or from either of the reference clock selection outputs. control bits determine the direction of the raclk and rasync signals and whether bposc or a selected receive line is used as a clock source when these signals are outputs. input data, clock and frame are provided by input leads tadat, taclk, and tasync. control bits determine the direction of the taclk and tasync signals and whether bposc or a selected receive line is used as a clock source when these signals are outputs. - 22 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers lead diagram for 208-lead pbga package figure 2. e1fx8 TXC-03109 lead diagram for the 208-lead pbga package tbms a r p n m l k j h g f e d c b 1 2 3 5 6 7 8 9 10 11 12 13 14 15 trs tbdi tneg1 tneg2 lcs2 tclk1 highz d7 d4 vdda sel a0 a4 a6 a9 a11 sregt rtclk5 scout1 a10 a8 a5 a1 rdy/dtack d1 d5 lsdo scout2 rtsig5 rtfrm5 a12 a7 a3 rd /wr wr /lds gnd vdd bposc rtdat5 ttaix5 vdd a2 d0 d2 d3 d6 lsclk ttsig5 ttdat5 ttfrm5 ttclk5 rtfrm6 rtclk6 rtsig6 rtdat6 test ttsig6 rtclk7 rtfrm7 rtdat7 rtsig7 ttsig7 ttfrm7 ttdat7 ttaix7 rtfrm8 vdd ttfrm8 sysci tpos8 rclk7 vdd tpos7 rpos6 tclk6 rneg5 rneg4 lcs4 rneg3 vdd rneg2 rpos2 lcs1 tpos3 rpos3 tpos4 rclk4 tpos5 rclk5 tneg6 lcs7 tneg7 rneg8 ttdat8 rtsig8 rtclk8 ttaix8 ttsig8 rtdat8 ttclk7 rclk6 tpos6 rpos5 tclk5 lcs5 tneg4 rclk3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnda gnd gnd gnd gnd gnd notes: this is the bottom view. the leads are solder balls. see figure 67 for package information. some signal symbols have been abbreviated to fit the space available. the ?a? designation for vdd and gnd indicate ?analog?. t 16 tclk7 lcs8 tclk8 gnd tneg8 rpos8 rclk8 ttclk8 gnd ttclk6 ttfrm6 vdd ttdat6 ttaix6 vdd reset int/ irq tpos1 tbck tbdo rclk1 rneg1 lcs3 tneg3 4 rpos1 rtclk1 e208 ttaix1 moto ttaix2 ttclk2 vdd ttsig3 ttclk3 vdd rtsig4 vdd config1 ttsig1 ttclk1 rtsig2 ttsig2 rtfrm3 ttdat3 rtfrm4 gnd rtdat4 ttaix4 ttclk4 ttfrm4 ttdat4 gnd ttsig4 lsdi rtdat3 rtclk3 ttdat2 rtdat1 rtfrm2 ttfrm1 gnd rtsig1 dpllref rtclk4 ttfrm3 ttaix3 rtsig3 ttfrm2 rtdat2 rtclk2 ttdat1 config0 rtfrm1 tclk2 tpos2 rpos7 rneg7 rneg6 lcs6 tneg5 rpos4 tclk4 pwdn tclk3 rclk2 - 23 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers lead diagram for 256-lead pbga package figure 3. e1fx8 TXC-03109 lead diagram for the 256-lead pbga package gnd a r p n m l k j h g f e d c b 123 5678 9 101112131415 spare trs rneg1 spare spare rclk1 highz radat mondat reset gnda a4 spare a10 a11 spare spare spare spare spare a12 a8 a5 a2 a0 lsclk bposc lsdi rtsig5 sregt scout1 spare a9 a3 a1 monclk scout2 ttfrm4 ttaix5 rtaux5 rtclk5 spare a6 gnd gnd ttclk4 vdd ttfrm5 ttdat5 rtdat5 rtfrm5 rtfrm6 ttclk5 ttaux5 vdd rtclk6 ttaix6 gnd rtfrm8 rtclk8 ttclk7 rtsig8 rtaux8 rtdat8 ttaux8 ttaix8 ttfrm8 rpos8 spare spare tpos8 spare rneg7 lcs7 rpos6 tpos6 rclk3 rneg3 tclk3 rneg2 lcs2 spare tbdo tneg2 rclk2 tneg3 rpos3 tneg6 spare tneg7 rclk7 spare spare ttclk8 ttdat8 ttsig8 rclk8 gnd sysci vdd tclk8 vdd tpos7 gnd gnd lcs3 vdd notes: this is the bottom view. the leads are solder balls. see figure 68 for package information. some signal symbols have been abbreviated to fit the space available. the ?a? designation for vdd and gnd indicate ?analog?. t 16 tclk7 spare spare spare rneg8 tneg8 spare gnd rtdat6 ttdat6 ttsig5 rtaux6 rtsig6 gnd a7 vdd tclk1 tbdi spare tbck tbms gnd spare 4 rpos1 lcs1 rtsig1 config0 ttsig2 rtclk3 rtaux3 ttaux3 rtfrm4 spare spare dpllref tneg1 rtclk1 e208 ttfrm2 rtfrm3 ttaix3 ttsig3 taclk tasync rtsig4 rtdat4 ttaux4 monfrm ttsig4 ttaix4 ttdat4 ta dat rtaux4 gnd rtclk4 vdd tpos1 rtdat3 gnd gnd vdd rasync raclk ttclk3 ttfrm3 ttdat3 rtsig3 ttclk2 ttaux2 config1 rtaux1 rtfrm1 spare tclk2 lcs8 rpos7 rclk6 rneg6 tclk6 lcs4 pwdn tpos3 rpos2 tpos2 lcs5 rpos4 rclk4 vdd spare tclk5 tpos5 tneg5 lcs6 rclk5 rpos5 rneg5 tclk4 tpos4 tneg4 rneg4 ttdat1 ttclk1 rtsig2 rtdat2 ttaix1 ttfrm1 rtfrm2 ttaix2 ttdat2 vdd ttsig1 rtdat1 rtaux2 rtclk2 moto ttaux1 d4 d3 d2 vdda vdd d1 d0 wr /lds rd /wr sel dtack int/irq d5 d6 d7 lsdo ttsig7 rtdat7 rtclk7 test ttaux7 ttaix7 rtfrm7 ttsig6 ttfrm6 rtsig7 rtaux7 ttdat7 ttaux6 ttclk6 vdd ttfrm7 17 18 19 20 w v u y - 24 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers lead descriptions the interface signal leads are ttl inputs and cmos 2 ma outputs, unless otherwise noted. also, the high impedance test mode requires all output leads to operate as tristate outputs, however, the leads are not speci- fied as such. the use of internal pull-up resistors is noted for input leads by use of the type suffix ?p? as required. the e1fx8 is packaged in a 256-lead plastic ball grid array with a 1.27 mm ball pitch and a 208-lead small outline plastic ball grid array with a 1.00 mm ball pitch. a ?t? designation in the ?i/o/p? column indicates tristate. symbol and lead number listings are in the same order in the table rows below. power supply, ground and spares * note: i = input; o = output; p = power; t = tristate; na = not available. line interface signals symbol 208-lead pbga lead no. 256-lead pbga lead no. i/o/p* name/function vdd b12, b15, c6, e2, g14, n2, n10, n13, p13, and t5 d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, and u15 p digital vdd: + 3.3 volt supply 5% vdda j16 k20 p analog vdd: + 3.3 volt supply 5% gnd c15, d8, e14, g7, g8, g9, g10, h7, h8, h9, h10, h14, j7, j9, j10, k7, k8, k9, k10, and n9 a1, d4, d8, d13, d17, h4, h17, n4, n17, u4, u8, u13, and u17 p digital ground: 0 volt reference gnda j8 p20 p analog ground: 0 volt reference spare none a2, b1, b2, b18, b19, c2, c3, d3, e4, l1, p3, t17, t20, u2, u3, u18, v3, v4, v19, w1, w2, w3, w19, w20, y1, y2, y19, and y20 - spare leads. these leads must not be connected to each other, to ground, or to any external circuit. connection could impair perfor- mance or cause damage. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type* name/function rposn/ rnrzn (n=1-8) a4, d3, f3, h1, k4, l2, p1, t3 a4, e1, h3, k2, m2, p2, u1, y4 i ttl receive unipolar positive signal input: when control bit rail (bit 7 in register x+00h) is a 1, the dual unipolar line interface is selected, and the rposn lead carries the receive positive rail input signal. rposn is high whenever a positive pulse is received. receive line nrz data input: when control bit rail (bit 7 in register x+00h) is a 0, the nrz line interface mode is selected and this lead carries the e1 data. rclkn (n=1-8) b4, d1, f4, h3, k3, m4, p2, r4 c5, f3, h2, k3, m3, r1, t3, v5 i ttl receive line clock input: the 2048 khz recovered clock input. control bit rxcp (bit 5 in register x+00h) determines the edge on which the positive/negative rail and nrz signals are to be clocked in on (rxcp = 1 for positive clock edge). * note: see input, output and i/o parameters section for type definitions. ttl p is a ttl input with a pull-up - 25 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers rnegn/ rscann (n=1-8) c4, d2, f2, h2, j2, l1, n1, r3 b5, e2, g2, j1, m1, p1, t2, y3 i ttl receive unipolar negative signal input: when con- trol bit rail (bit 7 in register x+00h) is a 1, the dual uni- polar line interface is selected, and the rnegn lead carries the receive negative rail input signal. rnegn is high whenever a positive pulse is received. receive scan input: when control bit rail (bit 7 in register x+00h) is a 0 and the fast sync option is not selected (control bit rxfs, bit 1 in register x+1ffh, is a 0), the rscann lead provides an input for indications of external bipolar violations or loss of signal detected in the external line interface transceiver as selected by control bit exlos (bit 3 in register x+00h). for code violations, a high indicates a bipolar violation and incre- ments the internal 16-bit coding violation counter. for loss of signal the active level is programmable using control bit elosn (bit 2 in register x+00h). the control selections are as follows (where x=don?t care): all inputs are clocked in on the active edge of the receive line clock rclkn. if unused, ground this lead. tposn/ tnrzn (n=1-8) a5, c1, e3, g3, j3, l4, m2, r2 d7, d1, f1, j3, l3, n2, p4, v2 ocmos 2ma transmit unipolar positive signal output: when con- trol bit rail (bit 7 in register x+00h) is a 1, the dual uni- polar mode is selected, and the tposn lead carries the transmit positive rail output signal. tposn is high when- ever a positive pulse is to be transmitted by the external line interface transceiver. transmit line (nrz) data output: when control bit rail (bit 7 in register x+00h) is a 0, the nrz mode is selected, and the tnrzn lead carries the transmit nrz data output signal. tnrzn is normally active high when- ever a positive or negative pulse is to be transmitted by the external line interface transceiver. when control bit txnrz (bit 2 in register x+05h) is a 1, the data output tnrzn is inverted and it is active low. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type* name/function rxfs exlos elosn lead function 0 0 x a high = one coding violation 0 1 0 los true when lead high 0 1 1 los true when lead low 1 0 x a high = last bit of multiframe 1 1 x do not use. - 26 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers tclkn (n=1-8) c5, b1, e1, g1, j4, k2, m1, t1 a5, c1, f2, j4, l2, n1, t1, t4 ocmos 2 ma transmit line clock: a 2048 khz clock output. the transmit 2048 khz line clock can be derived from a back- plane oscillator input (lead bposc), receive line clock (lead rclkn), or system clock (ttclkn). control bit txcp (bit 3 in register x+05h) determines the clock edge on which the transmit line signals tposn/tnegn and tnrzn are clocked out (txcp is set to a 1 for rising edge). tnegn/ tdrvn (n=1-8) b5, c2, e4, g4, j1, l3, n3, p3 c6, e3, g3, j2, l4, n3, r3, w4 ocmos 2 ma transmit unipolar negative signal output: when control bit rail (bit 7 in register x+00h) is a 1, the dual unipolar mode is selected, and the tnegn lead carries the transmit negative rail output signal. tnegn is high whenever a negative pulse is to be transmitted by the external line interface transceiver. transmit mode general purpose drive output: when control bit rail (bit 7 in register x+00h) is a 0 and con- trol bit tdfme (bit 7 of register x+07h) is a 0, the state written into control bit txdrv (bit 6 in register x+07h) is clocked out on active edges of the transmit line clock tclkn. transmit fast sync: when control bit rail (bit 7 in reg- ister x+00h) is a 0 and the fast sync mode is selected by control bit tdfme (bit 7 in register x+07h) set to a 1, this lead is used for a fast sync feature providing a sync pulse every frame or multiframe one tclkn clock cycle wide coincident with the first bit of a frame or multiframe (the frame bit) as determined by control bit tlmf (bit 5 of register x+07h). see the table below (where x=don?t care). symbol 208 pbga lead no. 256 pbga lead no. i/o/p type* name/function tdfme tlmf txdrv lead function 0 x 0 drive low 0x1drive high 1 1 x 2.0 ms multiframe pulse 10x125 s frame pulse - 27 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers line interface control signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function lsdi e13 (see monfrm below) f19 i/o ttl/ cmos 2 ma line interface transceiver data input signal: this lead provides an input data signal shared by all the lius controlled by the e1fx8. when using the 208-lead pack- age this lead is used by monfrm output when control bit espbmon (bit 5 in register 01dh) is set to a 1. lsdo g15 (see mondat below) j17 o cmos 4 ma line interface transceiver data output signal: this lead provides an output data signal shared with all the lius controlled by the e1fx8. when using the 208-lead package this lead is used by mondat when control bit espbmon (bit 5 in register 01dh) is set to a 1. lcsn (n=1-8) d5, c3, d4, g2, h4, k1, m3, r1 b6, d2, g4, h1, k1, m4, r2, v1 ocmos 2 ma line interface transceiver chip select output: an active low signal on a chip select lead indicates that the corresponding transceiver has been selected for com- munications between the transceiver and e1fx8. lsclk f13 (see monclk below) h19 o cmos 4 ma line interface transceiver clock output: this clock is used to clock input and output data between the e1fx8 and the external transceivers. this clock and the other timing signals for the liu interface are derived from the bposc signal. when using the 208-lead package this lead is used by monclk when control bit espbmon (bit 5 in register 01dh) is set to a 1. - 28 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers monitor interface signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function monclk f13 shares lsclk lead when global control bit espbmon = 1 h18 o cmos 2 ma monitor clock output: this clock is used to clock out one of the 8 receive or transmit channels selected. the 2048 khz clock is derived from either receive line clock or system transmit clock. the mon- itored data and framing pulse are clocked out on ris- ing edges of this clock. this lead is tristated if a 1 is written to control bit montr (bit 5 in register 022h). monfrm e13 shares lsdi lead when global control bit espbmon = 1 e20 o cmos 2 ma monitor framing pulse output: a one clock cycle wide positive framing pulse that represents the loca- tion of the framing bit, when the input or output of the receive or output of the transmit framer is selected by writing a 1 to control bits monrf and monrx (bits 6 and 7 in register 022h) or ia 0 to control bit monrx. this lead is also tristated when control bit montr (bit 5 in register 022h) is written with a 1. for test purposes the internally generated one-sec- ond clock can be brought out on this lead if control bit obt1si (bit 2 in register 0ffh) is set to a 1. mondat g15 shares lsdo lead when global control bit espbmon = 1 h20 o cmos 2 ma monitor data output: the data on this lead is either from the input to the receive framer, the output from the receive framer, or from the output of the transmit framer, prior to the codec. a 0 written to control bit monrx (bit 7 in register 022h) selects the transmit side. a 1 written to control bit monrx selects the receive side. a 1 written to control bit monrf (bit 6 in register 022h) selects the receive framer output. this lead is also tristated when control bit montr (bit 5 in register 022h) is written with a 1. - 29 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers reference clock input signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function bposc f14 g19 i ttl back plane external transmit clock/clock substitu- tion/liu input signal: this lead is used to input an independent transmit 2048 khz 50 ppm clock. this clock is used for internal transmit frame timing, clocking data/signaling out of the buffers, and a transmit clock. the transmit clock feature is enabled when control bits txc1,0 (bits 7 and 6 in register x+11ch) are set to 00. this clock, when enabled by control bit s1cien (bit 7 in register 00ch) set to a 1, is used for receive line clock substitution or for one-second clock source when a loss of signal alarm is detected on the receive line clock being used. this clock is used for deriving the timing signals needed for the external liu transceivers; it becomes lsclk. this clock can also be used to derive the one-second shadow register timing in place of sregt lead. global control bits s1sextb and s1sint (bits 4 and 3 in regis- ter 024h) set to 10 are used to select this lead as the source. this clock is required to operate the dpll for the dejitter buffers. sregt t16 w18 i/o ttl/ cmos 2 ma one-second shadow register input/output: a posi- tive one-second pulse ( 50 ppm when used for perfor- mance monitoring) can be applied to this lead when the shadow register feature or the ansi t1.403 ds0 remote loopback feature is enabled. global control bit s1sextb (bit 4 in register 024h) set to 0 is used to select this input for one-second timing. when control bit s1sextb is set to a 1, this lead becomes a one-second output signal. dpllref a16 b20 i/o ttlp/ cmos 8 ma dpll reference input/output: when the internal dpll is shut off (control bit disecksyn (bit 4) in register 0feh is set to a 1), this lead is used to input a 64512 khz 100 ppm (40 to 60% duty cycle) signal. this signal is used to operate the receive dejitter buffers. when the internal dpll is enabled (control bit disecksyn is set to a 0), this lead is used to output the 64512 khz (45 to 55% duty cycle) dpll reference clock signal which may be used to drive other e1fx8 devices. this clock is 31.5 times the frequency present at lead bposc and is used to operate the receive dejitter buffers. this lead has an internal pull-up resistor. - 30 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers synchronization clock output signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function scout1 r15 v18 o (t) cmos 2 ma synchronization clock output no. 1: a 2048 khz clock or an 8 khz signal (positive single 2048 khz clock cycle wide pulse, occurring every 125 s) which is derived from the receive clock framer input, for one of the 8 framers. control bits s1ync2-s1ync0 (bits 2 - 0 in register 024h) select the specific receive line clock. control bit s18khz (bit 7 in regis- ter 024h) when set to a 1 selects the 8 khz reference. an option is provided for enabling the 8 khz to be synchronous with the line framing bit, but delayed by the decoder. control bit synlf (bit 6 in register 00ch) when set to a 1 synchro- nizes this signal with the received framing bit position as the first bit of a frame in nrz mode for control bit rxcp (bit 5) in register x+00h set to 0; in ami or hdb3 it is the fourth bit of the frame. if rxcp is set to 1, this signal is aligned to the center of the last bit of the frame in nrz mode and the cen- ter of the third bit of the frame in ami or hdb3 mode. the alignments are delayed by 29.5 clock cycles with the dejitter buffers enabled. this lead is tristated when control bit s1ctri (bit 6 in register 024h) is set to 1. when a los occurs on the selected framer input this signal goes low if control bit s1yncen (bit 5 in register 024h) is set to a 1. the source selected by control bits s1ync2-s1ync0 can also be used to derive the one-second shadow register tim- ing in place of sregt. global control bits s1sextb and s1sint (bits 4 and 3 in register 024h) select the source. scout2 f15 g18 o (t) cmos 2 ma synchronization clock output no. 2: a 2048 khz clock or an 8 khz signal (positive single 2048 khz clock cycle wide pulse, occurring every 125 s) which is derived from the receive clock framer input, for one of the 8 framers. control bits s2ync2-s2ync0 (bits 2 - 0 in register 025h) select the specific receive line clock. control bit s28khz (bit 7 in regis- ter 025h) when set to a 1 selects the 8 khz reference. an option is provided for enabling the 8 khz to be synchronous with the line framing bit, but delayed by the decoder. control bit synlf (bit 6 in register 00ch) when set to a 1 synchro- nizes this signal with the received framing bit position as the first bit of a frame in nrz mode for control bit rxcp (bit 5) in register x+00h set to 0; in ami or hdb3 it is the fourth bit of the frame. if rxcp is set to 1, this signal is aligned to the center of the last bit of the frame in nrz mode and the cen- ter of the third bit of the frame in ami or hdb3 mode. the alignments are delayed by 29.5 clock cycles with the dejitter buffers enabled. this lead is tristated when control bit s2ctri (bit 6 in register 025h) is set to 1. when a los occurs on the selected framer input this signal goes low if control bit s2yncen (bit 5 in register 025h) is set to a 1. - 31 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers system interface signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function rtdatn (n=1-8) d7, a10, d13, c16, t13, n11, r8, n5 d9, b12, d14, c20, v16, v13, v10, v7 ocmos 2 ma; 8 ma for n=1,5 receive system data highway output: this lead out- puts the e1 received data. the following table is a sum- mary of the receive data highway interface. rtfrmn (n=1-8) a6, d10, c12, c14, r14, t11, p8, t6 a6, c11, c14, b17, u16, y15, w11, v8 i/o ttl/ cmos 2 ma receive system framing pulse input/output: this signal is used for frame and multiframe synchronization input. the following table summarizes the frame pulse characteristics used for the system side interfaces. leads conf0 and conf1 determine the modes. the e1fx8 can also be configured to source the clock and framing pulse for the transmission and data inter- faces only. control bit rxcke (bit 7 in register x+11bh) when set to a 1 causes the e1fx8 to source rtfrmn. interface format 2.048 mbit/s transmission e1 multiframe format (32 channels, 16 frames). 2 mbit/s mvip e1 frame carried in 31 time slots in a 32 time slot format. 8 mbit/s h-mvip/h.100 four e1 frames carried in four mvip frame formats that are byte-interleaved (n = 1, 5). 2.048 mbit/s data e1 frame format (32 channels) interface width polarity period lead used 2.048 mbit/s transmission 1 clk cyc. pos. 2 ms rtfrmn 2 mbit/s mvip 1 clk cyc. neg. 125 srtfrmn 8 mbit/s h-mvip/h.100 2,4 clk cyc neg. 125 s rtfrm1,5 2.048 mbit/s data 1 clk cyc. pos. 125 srtfrmn - 32 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers rtclkn (n=1-8) b6, a9, d12, a15, t15, r11, n8, p6 c7, a11, b14, d16, v17, v14, v11, w8 i/o ttl/ cmos 2 ma receive system clock input/output: a 2048/ 16384 khz clock that is clock for the received data, signaling, auxiliary, and framing pulse. the following table is a summary of the clock rates and transitions used for clocking data, signaling, rtauxn signal and framing pulse (when sourced). the e1fx8 can also be configured to source the clock and framing pulse for the transmission and data inter- faces only. control bit rxcke (bit 7 in register x+11bh) when set to a 1 causes the e1fx8 to source rtclkn. rtsign (n=1-8) d6, c10, a12, b16, t14, p11, t8, r6 (see rtauxn below) b7, b11, a15, c19, y18, w14, y11, y7 ocmos 2 ma; 8 ma for n=1,5 receive signaling highway output: this lead carries the e1 signaling states for data time slots. the following table provides information about the format of this signal. when using the 208-lead package this lead is used by rtauxn when control bit fe1m (bit 4 in register x+07h) is set to a 1. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function interface rate clk out clk in lead used 2.048 mbit/s transmission 2.048mhz. neg. neg. rtclkn 2 mbit/s mvip 2.048 mhz - pos. rtclkn 8 mbit/s h-mvip/h.100 16.384 mhz - neg. rtclk1,5 2.048 mbit/s data 2.048 mhz neg. neg. rtclkn interface format 2.048 mbit/s transmission time slot 1 carries fas and nfas framing including rai; time slot 2 carries signaling for two data time slots; 30 time slots carry an ais indication; a 16 frame structure covers 120 signaling bits. 2 mbit/s mvip signaling per data time slot carried in the lower nibble of 30 time slots in a 32-time slot format each frame plus optional fas/nfas framing carried in time slot 0. 8 mbit/s h-mvip/h.100 same as a mvip, except four signaling highways are byte-interleaved (n = 1, 5). 2.048 mbit/s data signaling per data time slot carried in 30 time slots each frame plus optional fas/nfas framing carried in time slot 0. - 33 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers rtauxn (n=1-8) d6, c10, a12, b16, t14, p11, t8, r6 shares rtsign lead when control bit fe1m (bit 4, reg. x+07h) = 1 a7, a12, b15, e17, w17, y14, y10, w7 ocmos 2 ma receive system auxiliary output: this lead is enabled for the transmission and data interfaces only. this signal lead can be programmed to provide a gapped clock or channel marker for one or more frac- tional time slots; see control bits rfch1-32 (registers x+1bh, x+1ch, x+1dh and x+1eh) and rchmk (bit 7 in register x+1ah). for testing purposes this lead can be selected by setting control bit oblol (bit 2 in register x+1ffh) to a 1 to output the state of the prbs analyzer (status bit tplol = 1 indicates out of lock and this lead will go high on a out of lock). ttdatn (n=1-8) a8, d11, c13, d15, r12, t10, p7, r5 b9, d12, a16, e18, w16, y13, y9, w6 i ttl transmit system data input: this lead inputs the e1 system side data for transmission on the e1 line. the fol- lowing table is a summary of the transmit data interface. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function interface format 2.048 mbit/s transmission e1 multiframe format (32 channels, 16 frames). 2 mbit/s mvip e1 frame carried in 31 time slots in a 32 time slot format. 8 mbit/s h-mvip/h.100 four e1 frames carried in four mvip frame formats that are byte-interleaved (n = 1, 5). 2.048 mbit/s data e1 frame format (32 channels) - 34 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers ttsign (n =1-8) c8, c11, b13, d14, t12, r9, t7, n4 (see ttauxn below) d10, b13, c16, e19, u14, w12, v9, v6 i/o ttl/ cmos 2 ma transmit signaling highway input: this lead carries the e1 signaling states for data time slots into the e1fx8. the following table provides information about the format of this signal. when using the 208-lead package this lead is used by ttauxn when control bit fe1m (bit 4 in register x+07h) is set to a 1. when used as ttauxn, this lead is an output. ttfrmn (n=1-8) d9, a11, a14, e15, p12, t9, r7, t4 c10, c13, a17, f18, y16, y12, u9, y5 i ttl transmit system framing pulse input: this signal is used for frame and multiframe synchronization. the fol- lowing table is a summary of the frame pulse character- istics used for the various system side interfaces. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function interface format 2.048 mbit/s transmission time slot 1 carries fas and nfas fram- ing including rai; time slot 2 carries sig- naling for two data time slots; 30 time slots carry an ais indication; a 16 frame struc- ture covers 120 signaling bits. 2 mbit/s mvip signaling per data time slot carried in the lower nibble of 30 time slots in a 32 time slot format each frame plus optional fas/nfas framing carried in time slot 0. 8 mbit/s h-mvip/h.100 same as a mvip, except four signaling highways are byte-interleaved (n = 1, 5). 2.048 mbit/s data signaling per data time slot carried in 30 time slots each frame plus optional fas/nfas framing carried in time slot 0. interface width polarity period lead used 2.048 mbit/s transmission 1 clk cyc. pos. 2 ms ttfrmn 2 mbit/s mvip 1 clk cyc. neg. 125 s ttfrmn 8 mbit/s h-mvip/h.100 2,4 clk cyc neg. 125 s ttfrm1,5 2.048 mbit/s data 1 clk cyc. pos. 125 s ttfrmn - 35 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers ttclkn (n=1-8) c9, b11, b14, e16, n12, p9, n6, p4 b10, a14, a18, g17, w15, u11, y8, w5 i ttl transmit system clock input: a 2048/16384 khz clock that is clock for the data, signaling, auxiliary, and framing pulse. this clock is also used to clock out the gapped clock or channel marker for fractional e1 chan- nels. the following table is a summary of the clock rates and transitions used for clocking in data, signaling, and framing pulse or clocking out the ttauxn signal. the gapped clock or channel marker (ttauxn) for selected e1 channels is clocked out on the listed transi- tions of this clock, one clock cycle earlier than the bit time required. ttauxn (n=1-8) c8, c11, b13, d14, t12, r9, t7, n4 shares ttsign lead when control bit fe1m (bit 4, reg. x+07h) =1 a9, a13, b16, d20, v15, u12, w9, u7 ocmos 2 ma transmit system auxiliary output: this lead is enabled for the transmission and data interfaces only. this signal lead can be programmed to provide a gapped clock or channel marker for one or more frac- tional e1 time slots; see control bits tc0c0-tc0c31 (even bits of registers x+111h - x+118h), tc1c0- tc1c31 (odd bits of registers x+111h - x+118h) and tchmk (bit 7 of register x+110h). ttaixn (n=1-8) b8, b10, a13, d16, r13, r10, n7, p5 c9, c12, c15, d19, y17, w13, w10, y6 i ttl transmit system auxiliary input: a signal input lead for multiplexing in the data from one or more fractional e1 time slots. it behaves like ttdatn but each time slot on this lead replaces the time slot (c = 0 - 31) on ttdatn if control bits tc1cc, tc0cc (registers x+111h - x+118h) are set to 01. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function interface rate gapout clk in lead used 2.048 mbit/s transmission 2.048 mhz pos. pos. rtclkn 2 mbit/s mvip 2.048 mhz - neg. rtclkn 8 mbit/s h-mvip/h.100 16.384 mhz - pos. rtclk1,5 2.048 mbit/s data 2.048 mhz pos. pos. rtclkn - 36 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers other control signals symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function highz f16 f20 i ttlp high impedance select input: a low forces all output leads (except tbdo) to the high impedance state for board testing purposes. this lead must be held high for normal operation. this lead has an internal pull-up resistor. test p10 v12 i ttlp transwitch test select input: used for manufacturing test purposes only. this lead must be tied high for nor- mal operation. this lead has an internal pull-up resistor. reset l14 n20 i ttl reset: an active low signal for resetting and initializing the internal counters and logic circuits for all 8 framers to their preset values. the reset must be applied only after power is applied and the clocks are stable for a minimum of 10 sysci pulses. pwdn f1 g1 i ttlp power down: an activate low on this lead forces the transmit line clocks (tclkn), and the transmit line inter- face leads (tposn/tnegn or tnrzn/tdrvn) to the active low state. the active low overrides the software power down control bits. this lead must be held high during power up of the e1fx8. this lead has an internal pull-up resistor. conf0 conf1 a7, c7 b8, a8 i ttl system side configuration selection: selects the e1fx8 system side interface configuration according to the following table (where x=don?t care): control bit dintf is bit 1 in register 00bh. system interface conf1 conf0 dintf 2mbit/s transmission l l 0 2 mbit/s mvip l h x 8 mbit/s h-mvip h l 0 8 mbit/s h.100 h l 1 2 mbit/s data l l 1 not used h h x - 37 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan e208 b7 (vdd) c8 (gnd) i ttl enable small package input: an active low on this lead selects the 256-lead version of the e1fx8; it must be tied to a ground lead with this package. control bits fe1m (bit 4 in register x+07h) and espbmon (bit 5 in register 01dh) have no effect on the function of leads rtsign, ttsign, lsclk, lsdi, or lsdo. an active high signal on this lead selects the 208-lead version of the e1fx8 enabling the control bits fe1m (which selects between signaling or gapped clock oper- ation on leads rtsign and ttsign) and espbmon (which selects between the line interface control option and the monitor mode function on leads lsclk, lsdi and lsdo). when common control bit espbmon is set to a 1, the monitor mode function is selected. when per framer control bit fe1m is set to a 1, the marker/gapped clock function is selected for that particular framer. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function tbck a3 b4 i ttl ieee 1149.1 test port serial scan clock input: the input clock for boundary scan testing. the tbdi and tbms states are clocked into the on rising edges. the maximum clock frequency is 10 mhz. tbdi b3 a3 i ttlp ieee 1149.1 test port serial scan data input: serial test instructions and data are clocked in on the rising edges of tbck. this lead has an internal pull-up resis- tor. tbdo a2 d5 o/(t) cmos 4 ma ieee 1149.1 test port serial scan data output: serial data output whose information is clocked out on falling edges of tbck. when inactive this output is forced to the high impedance state. tbms a1 c4 i ttlp ieee 1149.1 test port mode select input: this signal is clocked in on rising edges of tbck and is used to place the test access port controller into various states as defined in the ieee 1149.1 standard. this lead must be set high for normal framer operation. this lead has an internal pull-up resistor. trs b2 b3 i ttlp ieee 1149.1 test port reset input: an active low signal that provides for synchronization of the test access port (tap) controller. this lead is to be held low, asserted low or pulsed low to reset the tap controller on e1fx8 power up. this lead has an internal pull-up resistor. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function - 38 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function moto b9 a10 i ttl motorola/intel microprocessor select: a high selects a motorola (m mode) microprocessor compatible bus interface. a low selects the intel (i mode) microproces- sor compatible bus interface. a(12-0) p14,r16, p15, p16, n15, n14, n16, m15, m16, m14, m13, l15, l16 u19, v20, u20, t18, t19, r18, p17, r19, r20, p18, p19, n18, n19 i ttl address bus (motorola/intel buses) input: these are active high address line inputs that are used by the microprocessor for accessing a memory location for a read/write cycle. a12 is the most significant bit. d(7-0) g16, g13, h15, h16, h13, j13, j15, k13 j18, j19, j20, k17, k18, k19, l18, l19 i/o ttl/ cmos 8 ma data bus: bi-directional data lines used for transferring data between the e1fx8 and the microprocessor. d7 is the most significant bit. sel k16 m19 i ttlp select. a low enables data transfers between the micro- processor and the e1fx8 during a read/ write cycle.this lead has an internal pull-up resistor. rd rd/wr k14 m20 i ttl read (i mode) or read/write (m mode): intel mode - an active low signal generated by the microprocessor for reading the memory locations. motorola mode - an active high signal generated by the microprocessor for reading the 8-channel memory locations. an active low signal is used to write to the memory locations. wr/ lds j14 l20 i ttl write (i mode) or data strobe (m mode): intel mode - an active low signal generated by the microprocessor for writing to the e1fx8. motorola mode - an active low ds signal for motorola 68302 operation. this input can be grounded. rdy/ dtack k15 m18 o/(t) cmos 8 ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed ram location that the transfer can be completed. a low indicates that the device cannot complete the transfer cycle, and microprocessor wait states must be generated. motorola mode - during a read bus cycle, a low signal indicates the information on the data bus is valid. during a write bus cycle, a low sig- nal acknowledges the acceptance of data. int/ irq l13 m17 o cmos 4 ma interrupt: intel mode - a high on this output lead signals an interrupt request to the microprocessor. motorola mode - a low on this lead signals an interrupt request to the microprocessor. - 39 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers sysci t2 u5 i ttl system clock input: asynchronous clock input used for internal functions. this clock is usually connected to the microprocessor clock, and should be capable of operating between 19 and 25 mhz with a 40 to 60% duty cycle. this clock is not required to be synchronous with other clocks. this frequency range will provide correct operation with an e1 signal that complies with the fre- quency range and jitter as specified in itu-t g.703 and g.823. when the e1fx8 is used in a gapped clock situa- tion (e.g. a direct connection to the txc-03361, e123mux e1 ports), sysci minimum frequency must guarantee that at least 9 rising edges of sysci occur between any two rising or falling edges of any particular rclkn. the following table can be used to determine sysci frequency: symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function rclkn minimum t cyc (ns) sysci minimum frequency (mhz) 480 19 456 20 435 21 - 40 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers auxiliary port symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function raclk na a19 i/o ttlp/ cmos 2 ma receive auxiliary clock i/o: a 2.048 mhz clock signal used to clock out the data on lead radat. this clock may be derived from one of the 8 rclk leads, lead bposc or it may be selected as an input under direction of control bits racksel and radirsel (bits 1 and 0) in register 037h as shown in the table (where x=don?t care): when raclk is an output it clocks out rasync. this lead has an internal pull-up resistor. rasync na a20 i/o ttlp/ cmos 2 ma receive auxiliary frame synchronization: a 125 microsecond synchronization positive pulse signal for a single raclk clock cycle coincident with the first bit of the first time slot on radat. control bits racksel and radirsel (bits 1 and 0) in register 037h as shown in the table for raclk control the source and directionality of this signal. this lead has an internal pull-up resistor. radat na g20 o cmos 2 ma receive auxiliary data output: a data highway with 32 64 kbit/s time slots repeated at a 125 microsecond rate. each time slot may come from any one of 8 receive line ports (any time slot) or from any one of 8 transmit system interface ports (any time slot). control bits rdir31-0 in registers 038h through 03bh determine the source port side for each time slot; for rdirc set to 0 the source port side is the receive line (rposn/rnrzn and rnegn); for rdirc set to 1 the source port side is the transmit system (ttdatn) where n = 1 to 8 and c = 0 to 31. the individual time slot source is determined by control bits rafrselc(2-0) and ratsselc(5-0) in registers 040h through 05fh. rafrselc(2-0) selects ports 1 through 8 (000 selects framer port 1 and 111 selects framer port 8) and ratsselc(4-0) selects time slots 0 through 31 (00000 selects time slot 0 and 11111 selects time slot 31) on the selected port. racksel radirsel raclk (rasync) x 0 input: 2.048 mhz (125 s.) 1 1 output: from bposc 0 1 output: from rclkn; s1ync2-s1ync0 selects the received line clock - 41 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers taclk na c17 i/o ttlp/ cmos 2 ma transmit auxiliary clock i/o: a 2.048 mhz clock signal used to clock in the data on lead tadat. this clock may be derived from one of the 8 rclk leads, lead bposc or it may be selected as an input under direction of con- trol bits tacksel and tadirsel (bits 3 and 2) in reg- ister 037h as shown in the table (where x=don?t care): when taclk is an output it clocks out tasync. this lead has an internal pull-up resistor. tasync na c18 i/o ttlp/ cmos 2 ma transmit auxiliary frame synchronization: a 125 microsecond synchronization positive pulse signal for a single taclk clock cycle coincident with the first bit of the first time slot on tadat. control bits tacksel and tadirsel (bits 3 and 2) in register 037h as shown in the table for taclk control the source and directionality of this signal. this lead has an internal pull-up resistor. tadat na d18 i ttl p transmit auxiliary data input. a data highway with 32 64 kbit/s time slots repeated at a 125 microsecond rate. each time slot may go to any one of 8 transmit line ports any time slot or to any one of 8 receive system interface ports any time slot. control bits tdir31-0 in registers 03ch through 03fh determine the destination port side for each time slot; for tdirc set to 0 the destination port side is the transmit line (tposn/tnrzn and tnegn); for tdirc set to 1 the destination port side is the receive system (rtdatn) where n = 1 to 8 and c = 0 to 31. the individual time slot destination is determined by control bits tafrselc(2-0) and tatsselc(5-0) in registers 060h through 07fh. tafrselc(2-0) selects ports 1 through 8 (000 selects framer port 1 and 111 selects framer port 8) and tatsselc(4-0) selects time slots 0 through 31 (00000 selects time slot 0 and 11111 selects time slot 31) on the selected port. this lead has an internal pull-up resistor. symbol 208 pbga lead no. 256 pbga lead no. i/o/p type name/function tacksel tadirsel taclk (tasync) x 0 input: 2.048 mhz (125 s.) 1 1 output: from bposc 0 1 output: from rclkn; s1ync2-s1ync0 selects the received line clock - 42 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883d, method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +3.9 v note 1 dc input voltage v in -0.5 +5.5 v note 1 storage temperature range t s -55 +150 o cnote 1 ambient operating temperature t a -40 +85 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 100 % non-condensing esd classification esd absolute value 2000 v note 3 parameter min typ max unit test conditions 208-lead pbga thermal resis- tance: junction to ambient 38.0 o c/w 0 ft/min linear airflow 256-lead pbga thermal resis- tance: junction to ambient 25.0 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 3.15 3.30 3.45 v i dd (outputs loaded) 148 3 163 1 225 2 ma 1. all channels operating. output load 30 pf. sysci at 20 mhz. transmission, data or mvip mode. 2. all channels operating. output load 30 pf. sysci at 25 mhz. h-mvip mode @ 85 o c. 3. same as 1, except sysci at 19 mhz. p dd (outputs loaded) 470 3 540 1 776 2 mw i dd (outputs loaded) 152 ma all channels powered down (lead pwdn low). output load 30 pf. sysci at 19 mhz. p dd (outputs loaded) 500 mw - 43 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers input, output and input/output parameters input parameters for ttl input parameters for ttlp output parameters for cmos 2ma output parameters for cmos 4ma parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current -10 +10 a 0 to 5.25 v input input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current -30 -100 -500 a 0 to 5.25 v input input capacitance 5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -2.0 v ol 0.4 v v dd = 3.15; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tristate -10 +10 a 0 to 5.25 v input output capacitance 7.5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tristate -10 +10 a 0 to 5.25 v input output capacitance 7.5 pf - 44 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos 8ma (slew rate controlled) input/output parameters for ttl/cmos 2ma and ttlp/cmos 2ma input/output parameters for ttl/cmos 8ma and ttlp/cmos 8ma (slew rate controlled) parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -8.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf leakage tristate -10 +10 a 0 to 5.25 v input output capacitance 7.5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current ttl -10 +10 a 0 to 5.25 v input input leakage current ttlp -30 -100 -500 a 0 to 5.25 v input input capacitance 7.5 pf v oh v dd - 0.5 v v dd = 3.15; i oh = -2.0 v ol 0.4 v v dd = 3.15; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current ttl -10 +10 a 0 to 5.25 v input input leakage current ttlp -30 -100 -500 a 0 to 5.25 v input input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 3.15; i oh = -8.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf - 45 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the e1fx8 are illustrated in figures 4 through 37, with values of the timing inter- vals tabulated below the waveform diagrams in each figure. all output times are measured with a maximum 25 pf load capacitance. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals, unless otherwise indicated. figure 4. dual unipolar (rail) receive interface timing notes: 1. rclkn is shown for control bit rxcp (bit 5) in register x+00h set to 0. data (rposn/rnegn) is clocked in on the rising edges of rclkn when control bit rxcp is a 1. 2. the minimum frequency of sysci must guarantee that at least 9 rising edges of sysci occur between any two consecutive rising or falling edges of any particular rclkn. parameter symbol min typ max unit rclkn clock period (see note 2) t cyc 435 488.3 ns rclkn high time t pwh 180 0.5 x t cyc ns rclkn low time t pwl 180 0.5 x t cyc ns rposn/rnegn setup time to rclkn t su 5.0 ns rposn/rnegn hold time after rclkn t h 15 ns t su rclkn rposn (input) rnegn (input) note: n=1- 8 t h t pwh t pwl t cyc - 46 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 5. dual unipolar (rail) transmit interface timing note: tclkn is shown for control bit txcp (bit 3) in register x+05h set to 1. data is clocked out on falling edges of tclkn when control bit txcp is a 0. parameter symbol min typ max unit tclkn clock period t cyc 488.3 ns tclkn duty cycle (t pwh /t cyc ) -- 455055% tposn/tnegn delay after tclkn t d 0 5.0 10 ns t d tclkn tposn t cyc (output) tnegn (output) note: n=1- 8 t pwh - 47 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 6. nrz receive interface timing (external transceiver) notes: 1. the above figure is valid when control bit rail (bit 7 in register x+00h) is set to a 0. 2. rclkn is shown for control bit rxcp (bit 5 in register x+00h) set to 0. rnrzn and rscann are clocked in on ris- ing edges of rclkn when control bit rxcp is a 1. the e1fx8 accepts an inverted rnrzn signal when control bit rxnrz (bit 4 in register x+00h) is a 1. control bit rxfs (bit 1 in register x+1ffh) must be set to 0 to use the rscann input for code violation counting. 3. the minimum frequency of sysci must guarantee that at least 9 rising edges of sysci occur between any two consecutive rising or falling edges of any particular rclkn. parameter symbol min typ max unit rclkn clock period (see note 2) t cyc 435 488.3 ns rclkn high time t pwh 180 0.5 x t cyc ns rclkn low time t pwl 180 0.5 x t cyc ns rnrzn/rscann setup time to rclkn t su 5.0 ns rnrzn/rscann hold time after rclkn t h 15 ns t pwh rclkn t cyc t pwl (input) t su t h rnrzn (input) t su t h rscann (input) note: n=1 - 8 external bipolar violation - 48 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 7. nrz transmit interface timing (external transceiver) notes: 1. the above figure is valid when control bit rail (bit 7 in register x+00h) is set to a 0. 2. tclkn is shown for control bit txcp (bit 3 in register x+05h) set to 1. tnrzn and tdrvn are clocked out on falling edges of tclkn when control bit txcp is a 0. the e1fx8 provides an inverted tnrzn signal when control bit txnrz (bit 2 in register x+05h) is a 1. 3. control bit tdfme (bit 6 in register x+07h) must be set to 0 to obtain the tdrvn output shown. parameter symbol min typ max unit tclkn clock period t cyc 488.3 ns tclkn duty cycle (t pwh /t cyc ) -- 455055% tnrzn/tdrvn delay after tclkn t d 0 5.0 10 ns t d tclkn t cyc (output) tnrzn (output) t d tdrvn (output) note: n=1 - 8 state determined by control bit txdrv (bit 6 in x+07h) t pwh - 49 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 8. nrz receive interface timing (fast sync mode) notes: 1. the above figure is valid when control bit rail (bit 7 in register x+00h) is set to a 0. 2. rclkn is shown for control bit rxcp (bit 5 in register x+00h) set to 0. data is clocked in on rising edges when con- trol bit rxcp is a 1. the e1fx8 will accept an inverted rnrzn signal when a 1 is written to control bit rxnrz (bit 4) in register x+00h). 3. the fast sync mode is selected by writing a 1 to control bit rxfs (bit 1 in register x+1ffh). parameter symbol min typ max unit rclkn clock period t cyc(1) 435 488.3 ns rclkn high time t pwh(1) 180 0.5 x t cyc(1) ns rclkn low time t pwl(1) 180 0.5 x t cyc(1) ns rnrzn/rscann setup time to rclkn t su 15 ns rnrzn/rscann hold time after rclkn t h 15 ns rscann period t cyc(2) 256 x 16 x t cyc(1) ns rscann pulse width high time t pw 0.5 x t cyc(1) 1 t cyc(1) 1.5 x t cyc(1) ns rnrzn rclkn (input) (input) t pwl(1) t pwh(1) t cyc(1) rscann (input) t su t h bit 256 bit 1 bit 256 bit 1 t cyc(2) t h t su note: n=1 - 8 t pw frame 16 frame f frame f+1 frame f + 16 frame 0 - 50 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 9. nrz transmit interface timing (fast sync mode) notes: 1. the above figure is valid when control bit rail (bit 7 in register x+00h) is set to a 0. 2. tclkn is shown for control bit txcp (bit 3 in register x+05h) set to 1. tnrzn/tdrvn is clocked out on falling edges of ltclkn when control bit txcp is set to 0. the e1fx8 will output an inverted tnrzn signal when control bit txnrz (bit 2 in register x+05h) is a 1. 3. the fast sync mode is selected by writing a 1 to control bit tdfme (bit 7 in register x+07h). parameter symbol min typ max unit tclkn clock period t cyc(1) 488.3 ns tclkn duty cycle t pwh(1) /t cyc(1) 45 50 55 % tdrvn delay after tclkn t d 010ns tdrvn pulse width high time t pw 1 t cyc(1) ns tdrvn period control bit tlmf = 0 t cyc(2) 256 x t cyc(1) ns tdrvn period control bits tlmf =1 t cyc(2) 256 x 16 x t cyc(1) ns tnrzn tclkn (output) (output) t cyc(1) tdrvn (output) bit 256 bit 1 bit 256 t pw t d t cyc(2) frame f+1 frame f note: n=1 - 8 t pwh(1) frame 1 (tlmf = 0) frame 16 (tlmf = 1) frame f + 1 (tlmf = 0) frame f + 16 (tlmf =1 ) frame 0 - 51 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 10. serial port write timing notes: 1. the serial port interface for the line interface transceiver is selected in the 208-lead package when control bit espbmon (bit 5 in register 01dh) is set to 0. 2. the clock period for lsclk is the same as that of the signal provided on the bposc input lead because lsclk is derived from the signal at bposc. parameter symbol min typ max unit lcsn pulse width high time t pw 300 ns lsclk clock period (see note 2) t cyc 480 488.3 ns lsclk high time t pwh 190 0.5 x t cyc ns lsclk low time t pwl 190 0.5 x t cyc ns lcsn delay after lsclk t d(1) 0 5.0 12 ns lsdo delay after lsclk t d(3) 0 5.0 10 ns lcsn delay after lsclk t d(2) 0 5.0 10 ns t pw t d(2) t d(3) t cyc t pwh lsclk t pwl lcsn lsdo (output) (output) (output) t d(1) lsb lsb msb address/command data byte byte note: n=1 - 8 - 52 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 11. serial port read timing notes: 1. the serial port interface for the line interface transceiver is selected in the 208-lead package when control bit espbmon (bit 5 in register 01dh) is set to 0. 2. the clock period for lsclk is the same as that of the signal provided on the bposc input lead because lsclk is derived from the signal at bposc. parameter symbol min typ max unit lsdi setup time to lsclk t su 10 ns lsdi hold time after lsclk t h 10 ns lcsn delay after lsclk t d(1) 0 5.0 10 ns lcsn delay after lsclk t d(2) 0 5.0 10 ns t d(2) lsclk lcsn lsdi (output) (output) (input) t d(1) t su t h - 53 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 12. monitor mode timing note: when control bit montr (bit 5 in control register 022h) is set to a 1 the monclk, mondto and monfrm leads are tristated. when montr is set to 0 the monitor function in the e1fx8 is enabled; for the 208-lead package control bit espbmon (bit 5 in register 01dh) must be set to 1 also. control bits mfr2 - mfr0 (bits 2 - 0 in register 022h) select the channel to be monitored. control bit monrx (bit 7 in register 022h) selects either the receive side or transmit side to be monitored; when monrx is set to a 0 the transmit framer output is monitored. writing a 1 to con- trol bit monrx and a 0 to control bit monrf (bit 6 in register 022h) monitors the receive signal at the input to the receive framer. writing a 1 to both control bits monrf and monrx monitors the receive signal at the output of the receive framer. parameter symbol min typ max unit monclk clock period t cyc 488.3 ns monclk high time t pwh 0.5 x t cyc ns monclk low time t pwl 0.5 x t cyc ns mondto delay after monclk t d(1) -1.0 5.0 ns monfrm delay after monclk t d(2) -1.0 5.0 ns mondto monclk (output) (output) t d(1) t pwl t pwh t cyc t d(2) monfrm (output) - 54 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 13. receive highway timing - transmission mode (recovered receive line clock) note: the transmission mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 0. the recovered receive line clock (rclkn) and an internal sync pulse are used to clock out data (rtdatn), signaling (rtsign), and the sync pulse (rtfrmn) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 1. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) enables/disables the receive slip buffer. the position of rtfrmn with respect to the rtdatn/rtsign sig- nals can be offset. the values written to control bits rfrm7 - rfrm0 (register 02eh) will determine the offset. rtfrmn is shown for an offset value equal to zero. parameter symbol min typ max unit rtclkn clock period t cyc 435 488.3 ns rtclkn low time t pwl 180 0.5 x t cyc ns rtclkn high time t pwh 180 0.5 x t cyc ns rtdatn/rtsign delay after rtclkn t d(1) 2.0 8.0 17 ns rtfrmn delay after rtclkn t d(2) 1.0 10 14 ns rtfrmn pulse width t pw 435 488.3 ns rtfrmn period t fcyc 256 x 16 x t cyc ns rtclkn rtdatn rtsign t d(1) t cyc rtfrmn bit 255 bit 256 (bit 8 of time slot 31) t pwl bit 1 (first bit of time slot 0) (output) (outputs) (output) t pwh t pw t d(2) note: n=1- 8 t fcyc - 55 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 14. receive highway timing - transmission mode (system clock) notes: 1. the transmission mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 0. a system side clock (rtclkn) and a sync pulse (rtfrmn) are used to clock out data (rtdatn) and signaling (rtsign) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 0. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) set to 1 enables the receive slip buffer. the position of rtfrmn with respect to the rtdatn/rtsign signals can be offset. the values written to control bits rfrm7 - rfrm0 (register 02eh) will determine the offset. rtfrmn is shown for an offset value equal to zero. 2. only one rising edge of rtclkn may occur during the time interval (t pw ) of the positive pulse for the rtfrmn input. parameter symbol min typ max unit rtclkn clock period t cyc 465 488.3 ns rtclkn low time t pwl 233 0.5 x t cyc ns rtclkn high time t pwh 233 0.5 x t cyc ns rtdatn/rtsign delay after rtclkn t d 5.0 15 28 ns rtfrmn setup time to rtclkn t su 10 ns rtfrmn hold time after rtclkn t h 15 ns rtfrmn pulse width (see note 2) t pw 1 x t cyc ns rtfrmn period t fcyc 256 x 16 x t cyc ns rtclkn rtdatn rtsign t cyc rtfrmn t pwl (input) (outputs) (input) t pwh note: n=1 - 8 t su t h t d bit 255 bit 256 bit 1 (first bit of time slot 0) t fcyc t pw - 56 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 15. transmit highway timing - transmission mode notes: 1. the transmission mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 0. the position of ttfrmn with respect to the ttdatn/ttsign/ttaixn signals can be offset. the values written to control bits tfrm7-tfrm0 (register 02fh) will determine the offset. ttfrmn is shown for an offset value equal to zero. 2. only one rising edge of ttclkn may occur during the time interval (t pw ) of the positive pulse for the ttfrmn input. parameter symbol min typ max unit ttclkn clock period t cyc 435 488.3 ns ttclkn low time t pwl 180 0.5 x t cyc ns ttclkn high time t pwh 180 0.5 x t cyc ns ttdatn/ttsign/ttaixn setup time to ttclkn t su(1) 12 ns ttdatn/ttsign/ttaixn hold time after ttclkn t h(1) 12 ns ttfrmn setup time to ttclkn t su(2) 12 ns ttfrmn hold time after ttclkn t h(2) 12 ns ttfrmn pulse width (see note 2) t pw 1 x t cyc ns ttfrmn period t fcyc 256 x 16 x t cyc ns ttclkn ttdatn ttsign t cyc ttfrmn bit 255 bit 256 t pwl bit 1 (first bit of time slot 0) (input) ttaixn (input) t pwh note: n=1 - 8 t su(2) t h(2) t su(1) t h(1) (inputs) t fcyc t pw - 57 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 16. receive highway timing - data mode (recovered receive line clock) note: the data mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1. the recovered receive line clock (rclkn) and an internal sync pulse are used to clock out data (rtdatn), signaling (rtsign), and the sync pulse (rtfrmn) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 1. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) enables/disables the receive slip buffer. the position of rtfrmn with respect to the rtdatn/rtsign signals can be offset. the values written to control bits rfrm7 - rfrm0 (register 02eh) will determine the offset. rtfrmn is shown for an offset value equal to zero. parameter symbol min typ max unit rtclkn clock period t cyc 435 488.3 ns rtclkn low time t pwl 180 0.5 x t cyc ns rtclkn high time t pwh 180 0.5 x t cyc ns rtdatn/rtsign delay after rtclkn t d(1) 2.0 8.0 17 ns rtfrmn delay after rtclkn t d(2) 1.0 8.0 14 ns rtfrmn pulse width t pw 435 488.3 ns rtfrmn period t fcyc 256 x t cyc ns rtclkn rtdatn rtsign t d(1) t cyc rtfrmn bit 256 bit 1 (first bit of time slot 0) t pwl bit 2 (output) (outputs) (output) t pwh t pw t d(2) note: n=1- 8 t fcyc - 58 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 17. receive highway timing - data mode (system clock) notes: 1. the data mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1. a system side clock (rtclkn) and a sync pulse (rtfrmn) are used to clock out data (rtdatn) and signaling (rtsign) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 0. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) set to 1 enables the receive slip buffer. the position of rtfrmn with respect to the rtdatn/rtsign signals can be offset. the values written to con- trol bits rfrm7-rfrm0 (register 02eh) will determine the offset. rtfrmn is shown for an offset value equal to zero. 2. only one rising edge of rtclkn may occur during the time interval (t pw ) of the positive pulse for the rtfrmn input. parameter symbol min typ max unit rtclkn clock period t cyc 465 488.3 ns rtclkn low time t pwl 233 0.5 x t cyc ns rtclkn high time t pwh 233 0.5 x t cyc ns rtdatn/rstign delay after rtclkn t d 5.0 15 28 ns rtfrmn setup time to rtclkn t su 10 ns rtfrmn hold time after rtclkn t h 15 ns rtfrmn pulse width (see note 2) t pw 1 x t cyc ns rtfrmn period t fcyc 256 x t cyc ns rtclkn rtdatn rtsign t cyc rtfrmn t pwl (input) (outputs) (input) t pwh note: n=1 - 8 t su t h t d bit 256 bit 1 (first bit of time slot 0) bit 2 t fcyc rtclkn rtdatn rtsign t cyc rtfrmn t pwl (input) (outputs) (input) t pwh note: n=1 - 8 t su t h t d bit 256 bit 1 (first bit of time slot 0) bit 2 t fcyc t pw - 59 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 18. transmit highway timing - data mode notes: 1. the data mode is selected when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1. the position of ttfrmn with respect to the ttdatn/ttsign/ttaixn signals can be offset. the values written to control bits tfrm7-tfrm0 (register 02fh) will determine the offset. ttfrmn is shown for an offset value equal to zero. 2. only one rising edge of ttclkn may occur during the time interval (t pw ) of the positive pulse for the ttfrmn input. parameter symbol min typ max unit ttclkn clock period t cyc 435 488.3 ns ttclkn low time t pwl 180 0.5 x t cyc ns ttclkn high time t pwh 180 0.5 x t cyc ns ttdatn/ttsign/ttaixn setup time to ttclkn t su(1) 12 ns ttdatn/ttsign/ttaixn hold time after ttclkn t h(1) 12 ns ttfrmn setup time to ttclkn t su(2) 12 ns ttfrmn hold time after ttclkn t h(2) 12 ns ttfrmn pulse width (see note 2) t pw 1 x t cyc ns ttfrmn period t fcyc 256 x t cyc ns ttclkn ttdatn ttsign t cyc ttfrmn bit 256 bit 1 (first bit of time slot 0) t pwl bit 2 (input) ttaixn (input) t pwh note: n=1 - 8 t su(2) t h(2) t su(1) t h(1) (inputs) t fcyc t pw - 60 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 19. receive highway timing - mvip mode notes: 1. the mvip mode is selected when a high is placed on conf0 lead and a low is placed on conf1 lead. a system side clock (rtclkn) and a sync pulse (rtfrmn) are used to clock out data (rtdatn) and signaling (rtsign) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 0. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) set to 1 enables the receive slip buffer. the position of rtfrmn with respect to the rtdatn/rtsign signals can be offset. the values written to control bits rfrm7 - rfrm0 (reg- ister 02eh) will determine the offset. rtfrmn is shown for an offset value equal to zero. 2. on rtdatn bit 256 is bit 8 of time slot 31. on rtsign bit 256 is the d signaling bit of time slot 31. 3. rtfrmn should not be held low for more than 10 rtclkn clock cycles under any circumstances. 4. when referring to mvip standards, bit 256 is bit 0 of time slot 31 (channel 31). bit 1 of the frame is bit 7 of time slot 0 (channel 0) and bit 2 of the frame is bit 6 of time slot 0 (channel 0). parameter symbol min typ max unit rtclkn clock period t cyc 465 488.3 513 ns rtclkn low time t pwl 220 0.5 x t cyc 268 ns rtclkn high time t pwh 220 0.5 x t cyc 268 ns rtdatn/rtsign delay after rtclkn t d 5.0 10 20 ns rtfrmn setup time to rtclkn t su 10 ns rtfrmn hold time after rtclkn t h 15 ns rtfrmn pulse width low time; (see note 3) t pw 200 488 500 ns rtfrmn period t fcyc 256 x t cyc ns rtclkn rtdatn rtsign t cyc rtfrmn bit 256 bit 1 (first bit of time slot 0) t pwh t d t pwl t h t su t pw (input) (outputs) (input) note: n=1 - 8 bit 2 (second bit of time slot 0) t fcyc (see notes 2,4) - 61 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 20. transmit highway timing - mvip mode notes: 1. the mvip mode is selected when a high is placed on conf0 lead and a low is placed on conf1 lead. the trans- mit slip buffer is always enabled in this mode by setting control bit txsbe (bit 5 in register x+11ch) to a 1. the position of ttfrmn with respect to the ttdatn/ttsign signals can be offset. the values written to control bits tfrm7 - tfrm0 (register 02fh) will determine the offset. ttfrmn is shown for an offset value equal to zero. 2. on ttdatn bit 256 is bit 8 of time slot 31. on ttsign bit 256 is the d signaling bit of time slot 31. 3. ttfrmn should not be held low for more than 10 ttclkn clock cycles under any circumstances. 4. when referring to mvip standards, bit 256 is bit 0 of time slot 31 (channel 31). bit 1 of the frame is bit 7 of time slot 0 (channel 0) and bit 2 of the frame is bit 6 of time slot 0 (channel 0). parameter symbol min typ max unit ttclkn clock period t cyc 480 488.3 497 ns ttclkn low time t pwl 220 0.5 x t cyc 268 ns ttclkn high time t pwh 220 0.5 x t cyc 268 ns ttdatn/ttsign setup time to ttclkn t su(1) 12 ns ttdatn/ttsign hold time after ttclkn t h(1) 12 ns ttfrmn setup time to ttclkn t su 10 ns ttfrmn hold time after ttclkn t h 10 ns ttfrmn pulse width low time; (see note 3) t pw 200 488 500 ns ttfrmn period t fcyc 256 x t cyc ns ttclkn ttdatn ttsign t cyc ttfrmn bit 1 (first bit of time slot 0) t pwh t pwl t h t su t pw (input) (inputs) (input) note: n=1 - 8 t su(1) t h(1) bit 2 (second bit of time slot 0) t fcyc bit 256 (see notes 2,3) - 62 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 21. receive highway timing - fractional e1 gapped clock (rec. line clock transmission & data modes) note: the fractional e1 gapped clock or marker feature is enabled when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1 for data mode or set to a 0 for transmission mode and con- trol bit fe1m (bit 4 in register x+07h) is written with a 1 when the 208-lead version is used. one or more time slots may be selected by writing a 1 to one or more control bits rfch1-rfch32 (in registers x+1bh-x+1eh). if control bit rchmk (bit 7 in register x+1ah) is set to a 1 a marker signal is provided in place of a gapped clock. parameter symbol min typ max unit rtclkn clock period t cyc 435 488.3 ns rtclkn low time t pwl 180 0.5 x t cyc ns rtclkn high time t pwh 180 0.5 x t cyc ns rtdatn delay after rtclkn t d(1) 2.0 8.0 12 ns rtauxn gapped clock delay after rtclkn t d(2) 1.0 8.0 ns rtfrmn delay after rtclkn t d(3) 1.0 6.0 10 ns rtauxn marker delay after rtclkn t d(4) 3.0 15 ns rtfrmn pulse width t pw 435 488.3 ns rtclkn (output) rtdatan (output) rtauxn (output) rtfrmn (output- 12345678910 t d(3) t pw t d(2) t pwl t pwh t cyc t d(1) time slot 0 selected 256 rtauxn (output) transmission mode) t d(4) rchmk = 0 rchmk = 1 note: n=1 - 8 - 63 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 22. receive highway timing - fractional e1 gapped clock (system clock transmission & data modes) note: the fractional e1 gapped clock or marker feature is enabled when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1 for data mode or set to a 0 for transmission mode and con- trol bit fe1m (bit 4 in register x+07h) is written with a 1 when the 208-lead version is used. one or more time slots may be selected by writing a 1 to one or more control bits rfch1-rfch32 (in registers x+1bh-x+1eh). if control bit rchmk (bit 7 in register x+1ah) is set to a 1 a marker signal is provided in place of a gapped clock. parameter symbol min typ max unit rtclkn clock period t cyc 465 488.3 ns rtclkn low time t pwl 180 0.5 x t cyc ns rtclkn high time t pwh 180 0.5 x t cyc ns rtdatn delay after rtclkn t d(1) 5.0 20 ns rtauxn gapped clock delay after rtclkn t d(2) 5.0 20 ns rtfrmn hold after rtclkn t su(1) 15 ns rtauxn marker delay after rtclkn t d(4) 5.0 25 ns rtfrmn setup before rtclkn t h(1) 10 ns rtclkn (input) rtdatan (output) rtauxn (gapped clk output) rtfrmn (input- 12345678910 t su(1) t h(1) t d(2) t pwl t pwh t cyc t d(1) time slot 0 selected 256 rtauxn (marker output) transmission mode) t d(4) rchmk = 0 rchmk = 1 note: n=1 - 8 - 64 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 23. transmit highway timing - fractional e1 gapped clock (transmission & data modes) note: the fractional e1 gapped clock or marker feature is enabled when a low is placed on both conf0 and conf1 leads with control bit dintf (bit 1 in register 00bh) set to a 1 for data mode or set to a 0 for transmission mode and con- trol bit fe1m (bit 4 in register x+07h) is written with a 1 when the 208-lead version is used. one or more time slots may be selected by writing a 01 to one or more control bit pairs tc1c0/tc0c0-tc1c31/tc0c31 (in registers x+111h-x+118h). if control bit tchmk (bit 7 in register x+110h) is set to a 1 a marker signal is provided in place of a gapped clock. inputs from the ttaixn lead replace time slots from the ttdatn lead for gapped clock or marker selections when control bit pairs tc1c0/tc0c0-tc1c31/tc0c31 are set to a 01. parameter symbol min typ max unit ttclkn clock period t cyc 422 488.3 ns ttclkn low time t pwl 190 0.5 x t cyc ns ttclkn high time t pwh 190 0.5 x t cyc ns ttdatn/ttaixn setup time to ttclkn t su(1) 12 ns ttdatn/ttaixn hold time after ttclkn t h(1) 12 ns ttfrmn setup time to ttclkn t su(2) 12 ns ttfrmn hold time after ttclkn t h(2) 12 ns ttauxn gapped clock output delay from ttclkn t d(1) 5.0 10 25 ns ttauxn marker output delay from ttclkn t d(2) 5.0 10 25 ns 12345678910 t pwl t pwh t cyc t su(1) for the time slot selected t d(1) ttclkn (input) ttdatn ttaixn ttauxn (gapped clk output) ttfrmn (input- t h(1) t h(2) t su(2) 256 (input) transmission mode) tchmk = 0 ttauxn (marker output) tchmk = 1 t d(2) note: n=1 - 8 - 65 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 24. receive highway timing - 8 mbit/s h-mvip/ h.100 mode notes: 1. the 8 mbit/s h-mvip/h.100 mode is selected when a low is placed on the conf0 lead and a high is placed on the conf1 lead. control bit dintf (bit 1 in register 00bh) is set to a 1 for h.100 mode or set to a 0 for h-mvip mode. a system side 16.384 mhz clock (rtclk1, 5) and a 125 microsecond sync pulse (rtfrm1, 5) are used to clock out data (rtdat1, 5) and signaling (rtsig1, 5) to the system, when control bit rxcke (bit 7 in register x+11bh) is set to a 0. control bit rxcke selects the clock source, while rxsbe (bit 5 in register x+11bh) set to 1 enables the receive slip buffer. the position of rtfrm1, 5 with respect to the rtdat1, 5/rtsig1, 5 signals can be offset in 8-clock cycle increments. the values written to control bits rfrm7 - rfrm0 (register 02eh) will determine the off- set. rtfrmn is shown for an offset value equal to zero. 2. rtfrmn should not be held low for more than 10 rtclkn clock cycles under any circumstances. 3. rtfrm1, 5 pulse widths may be wider than 4 x t cyc as long as no more than 4 rising edges of rtclk1, 5 occur while rtfrm1, 5 is low. 4. rtfrm1, 5 pulse widths may be wider than 2 x t cyc as long as no more than 2 rising edges of rtclk1, 5 occur while rtfrm1, 5 is low. parameter symbol min typ max unit rtclk1, 5 clock period t cyc 60 61 ns rtclk1, 5 low time t pwl 30 0.5 x t cyc ns rtclk1, 5high time t pwh 30 0.5 x t cyc ns rtdat1, 5/rtsig1, 5 delay after rclk1 , 5 t d 5.0 15 20 ns rtfrm1, 5 setup time to rclk1 , 5 ; hmvip t su(1) 10 ns rtfrm1, 5 hold time after rclk1 , 5 ; hmvip t h(1) 10 ns rtfrm1, 5 pulse width low time; hmvip (see note 3) t pw(1) 4 x t cyc 4 x t cyc <5 x t cyc ns rtfrm1, 5 setup time to rclk1 , 5 ; h.100 t su(2) 10 ns rtfrm1, 5 hold time after rclk1 , 5 ; h.100 t h(2) 10 ns rtfrm1, 5 pulse width low time; h.100 (see note 4) t pw(2) 2 x t cyc 2 x t cyc <3 x t cyc ns rtfrm1, 5 period t fcyc 2048 x t cyc ns rtfrm1, 5 (input: control bit dintf = 0) t d t h(1) t su(1) rtclk1, 5 (input) rtdat1, 5 rtsig1, 5 framer no. 4 time slot 31 bit 8 framer no. 1 time slot 0 bit 1 note: each group of four framers? time slots are byte-interleaved. (outputs) t cyc t pwh t pwl frame f + 1 frame f rtfrm1, 5 (input: control bit dintf = 1) t h(2) t su(2) t pw(2) t pw(1) t fcyc t fcyc framer no. 1 time slot 0 bit 2 framer no. 4 time slot 31 bit 7 - 66 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 25. transmit highway timing - 8 mbit/s h-mvip/ h.100 mode notes: 1. the 8 mbit/s h-mvip/h.100 mode is selected when a low is placed on the conf0 lead and a high is placed on the conf1 lead. control bit dintf (bit 1 in register 00bh) is set to a 1 for h.100 mode or set to a 0 for h-mvip mode. a system side 16.384 mhz clock ttclk1, 5) and a 125 microsecond sync pulse (ttfrm1, 5) are used to clock in data (ttdat1, 5) and signaling (ttsig1, 5) to the system. control bit txsbe (bit 5 in register x+11ch) always set to 1 enables the transmit slip buffer. the position of ttfrm1, 5 with respect to the ttdat1, 5/ttsig1, 5 signals can be offset in 8-clock cycle increments. the values written to control bits tfrm7-tfrm0 (register 02fh) will determine the offset. ttfrmn is shown for an offset value equal to zero. 2. ttfrmn should not be held low for more than 10 ttclkn clock cycles under any circumstances. 3. ttfrm1, 5 pulse widths may be wider than 4 x t cyc as long as no more than 4 rising edges of ttclk1, 5 occur while rtfrm1, 5 is low. 4. ttfrm1, 5 pulse widths may be wider than 2 x t cyc as long as no more than 2 rising edges of ttclk1, 5 occur while rtfrm1, 5 is low. parameter symbol min typ max unit ttclk1, 5 clock period t cyc 60 61 ns ttclk1, 5low time t pwl 30 0.5 x t cyc ns ttclk1, 5high time t pwh 30 0.5 x t cyc ns ttdat1, 5/ttsig1, 5 setup time to tclk1 , 5 t su(1) 15 ns ttdat1, 5/ttsig1, 5 hold time after tclk1 , 5 t h(1) 5.0 ns ttfrm1, 5 setup time to tclk1 , 5 ; hmvip t su(2) 15 ns ttfrm1, 5 hold time after tclk1 , 5 ; hmvip t h(2) 5.0 ns ttfrm1, 5 pulse width low time; hmvip (see note 3) t pw(1) 4 x t cyc 4 x t cyc <5 x t cyc ns ttfrm1, 5 setup time to tclk1 , 5 ; h100 t su(3) 15 ns ttfrm1, 5 hold time after tclk1 , 5 ; h100 t h(3) 5.0 ns ttfrm1, 5 pulse width low time; h100 (see note 4) t pw(2) 2 x t cyc 2 x t cyc <3 x t cyc ns ttfrm1, 5 period t fcyc 2048 x t cyc ns ttdat1, 5 ttclk1, 5 (input) ttsig1, 5 ttfrm1, 5 (input: control bit note: each group of four framers? time slots are byte-interleaved. (inputs) t cyc t pwl t pwh frame f + 1 frame f t h(2) t su(2) t pw(1) t h(1) t su(1) framer no. 1 time slot 0 bit 1 ttfrm1, 5 (input: control bit dintf = 1) t h(3) t su(3) t pw(2) dintf = 0) t fcyc t fcyc - 67 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 26. shadow register timing notes: 1. the shadow register feature and this input are enabled when a 1 is written to control bit srgen (bit 3 in register 00bh). this signal is selected when control bit s1sextb (bit 4 in register 024h) is set to a 0. 2. to meet itu-t g.823 requirements this clock must be 1.0 hz 50 ppm when used for performance monitoring. 3. sregt pulse width low can exceed this maximum value with a risk of overflow on the e-bit, crc-4 and sa6 code counters. 4. the actual cycle for sregt as an output is a function of the accuracy of the selected clock source. figure 27. dpll reference input/output timing parameter symbol min typ max unit sregt clock period (see notes 2,4) t cyc 1.0 s sregt (input) pulse width high t pwh 435 ns sregt (input) pulse width low (see note 3) t pwl 1020 ms sregt (output) pulse width high t pwh 488.3 ns sregt (output) pulse width low (see note 4) t pwl 1000 ms parameter symbol min typ max unit dpllref clock period t cyc 15.5 ns dpllref (input) pulse width high t pwh 6.2 ns dpllref (input) pulse width low t pwl 6.2 ns dpllref (output) pulse width high t pwh 7.0 ns dpllref (output) pulse width low t pwl 7.0 ns sregt (input or output) t pwl t pwh t cyc dpllref (input or output) t pwl t pwh t cyc - 68 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 28. boundary scan timing parameter symbol min max unit tbck clock high time t pwh 50 ns tbck clock low time t pwl 50 ns tbms setup time to tbck t su(1) 3.0 - ns tbms hold time after tbck t h(1) 2.0 - ns tbdi setup time to tbck t su(2) 5.0 - ns tbdi hold time after tbck t h(2) 7.0 - ns tbdo delay from tbck t d 3.0 15 ns tbms tbdi tbdo t d tbck (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl (input) - 69 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 29. intel microprocessor read cycle timing notes: 1. the intel microprocessor bus is selected by placing a low on the moto lead. 2. the system clock (sysci) has a nominal frequency of 19-25 mhz. parameter symbol min typ max unit a(12-0) valid setup time to sel t su(1) 5.0 ns d(7-0) valid delay before rdy t d(1) 10 ns d(7-0) float time after rd t f 2.0 15 ns sel setup time to rd t su(3) 5.0 ns sel hold time after rd t h(3) 7ns rd pulse width low time t pw(1) 50 ns rdy delay after rd t d(2) 3.0 17 ns rdy pulse width low time (see note 2) t pw(2) 1 cycle of sysci 2 cycles of sysci 10 cycles of sysci ns a(12-0) hold time after rd t h(2) 7ns rdy high to tristate delay after rd t d(4) 4.0 15 ns a(12-0) d(7-0) sel rd rdy t h(3) t f t d(1) t pw(2) t d(2) t su(3) t su(1) t pw(1) (input) (output) (input) (input) (output) tristate tristate t d(4) t h(2) - 70 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 30. intel microprocessor write cycle timing notes: 1. the intel microprocessor bus is selected by placing a low on the moto lead. 2. the system clock (sysci) has a nominal frequency of 19-25 mhz. 3. wait states only occur if a write cycle immediately follows a previous read/write cycle (e.g., read modify write or word wide write). 4. the timing is with respect to the earliest of wr or sel . 5. when writing to address x+127h (fdl transmit fifo) only, allow a minimum of 2 cycles of sysci between rdy and sel or wr parameter symbol min typ max unit a(12-0) valid setup time to sel t su(1) 5.0 ns a(12-0) hold time after wr , sel (see note 4) t h(1) 7.0 ns d(7-0) valid setup time to wr , sel (see note 4) t su(2) 10 ns d(7-0) hold time after wr , sel (see note 4) t h(2) 7.0 ns sel setup time to wr t su(3) 5.0 ns wr pulse width low time/ sel pulse width low time t pw(1) 50 ns rdy delay after wr t d(2) 3.0 17 ns rdy pulse width low time (see notes 2, 3) t pw(2) 0 cycles of sysci 7 cycles of sysci 10 cycles of sysci ns rdy high to tristate delay after earliest of wr or sel t d(4) 17 35 ns rdy high to wr , sel (see note 4) t su(4) 0.0 ns sel hold time after wr t h(3) 7.0 ns rdy hold time after wr or sel (see note 5) t h(4) 2 cycles of sysci ns a (12-0) d(7-0) sel wr rdy t h(2) t su(1) t pw(2) t d(2) t su(3) t pw(1) t su(2) t h(1) (input) (input) (input) (input) (output) tristate tristate t d(4) t su(4) t h(3) t h(4) - 71 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 31. motorola microprocessor read cycle timing notes: 1. the motorola microprocessor bus is selected by placing a high on the moto lead. 2. the system clock (sysci) has a nominal frequency of 19-25 mhz. 3. setup time t su(1) / t su(3) /t d(2) min. is the latter of lds or sel ; delay to tristate t d(3) /t f is the earlier of ld s or sel . parameter symbol min typ max unit a(12-0) valid setup time to sel /lds (see note 3) t su(1) 10 ns a(12-0) hold time to sel /lds (see note 3) t h 7.0 ns d(7-0) delay to tristate after sel /lds (see note 3) t d(3) 3.0 15 ns d(7-0) valid output delay after dtack (see note 2) t d(1) -1 cycle of sysci -1/4 cycle of sysci ns sel or lds pulse width low time t pw(1), t pw(2) 50 ns rd/wr setup time to sel / lds (see note 3) t su(3) 10 ns dtack pulse width high time (see note 2) t pw(2) 2 cycles of sysci 10 cycles of sysci ns dtack float time after sel /lds (see note 3) t f 4.0 12 ns dtack delay after sel /lds (see note 3) t d(2) 4.0 15 ns a(12-0) d(7-0) sel rd/wr dtack t f t d(3) t d(1) t pw(2) t su(3) t su(1) t pw(1) t d(2) (input) (output) (input) (input) (output) tristate tristate lds (input) t pw(2) t h - 72 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 32. motorola microprocessor write cycle timing parameter symbol min typ max unit a(12-0) valid setup time to lds , sel (see note 4) t su(1)/ t su(4) 10 ns a(12-0) hold time after lds , sel (see note 5) t h(1) 7.0 ns d(7-0) valid setup time to lds , sel (see note 5) t su(2) 10 ns sel pulse width low time t pw(1) 50 ns d(7-0) hold time after lds , sel (see note 5) t h(2) 7.0 ns rd/wr setup time to lds , sel (see note 4) t su(3) 10 ns dtack pulse width high time (see notes 2, 3) t pw(2) 0 cycles of sysci 10 cycles of sysci ns dtack float time after lds , sel (see note 5) t f 3.0 15 ns dtack delay after lds , sel (see note 4) t d(2) 4.0 17 ns rd/wr hold time to lds , sel (see note 4) t h(3) 10 ns lds pulse width low time t pw(3) 50 ns dtack low to lds , sel (see note 5) t su(5) 0.0 ns dtack to sel or rd/wr (see note 6) t h(4) 2 cycles of sysci ns a(12-0) d(7-0) sel rd/wr t f t pw(2) t su(1) t su(3) dtack t su(2) t h(2) t pw(1) t d(2) t h(1) (input) (input) (input) (input) (output) tristate tristate lds (input) t su(4) t pw(3) t h(3) t su(5) t h(4) - 73 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the motorola microprocessor bus is selected by placing a high on the moto lead. 2. the system clock (sysci) has a nominal frequency of 19-25 mhz. 3. wait states only occur if a write cycle immediately follows a previous read/write cycle (e.g., read modify write or word wide write). 4. measured with respect to the latter of lds or sel falling edge. 5. measured with respect to the earlier of sel or lds rising edge. 6. when writing to address x+127h (fdl transmit fifo) only, allow a minimum of 2 cycles of sysci between dtack and sel or rd/wr - 74 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 33. clock reference timing notes 1. scout1 and scout2 output leads are controlled by registers 024h and 025h respectively. control bit s18khz (bit 7 in register 024h) selects either a direct clock output for scout1 when set to 0 or via a divide by 256 circuit when set to 1. control bit s28khz (bit 7 in register 025h) selects either a direct clock output for scout2 when set to 0 or via a divide by 256 circuit when set to 1. control bits s1ctri (bit 6 in register 024h) and s2ctri (bit 6 in register 025h) enables output leads scout1 and scout2 when set to 0; when s1ctri and s2ctri are set to 1 scout1 and scout2 are tristated. the particular receive clock rclkn used as a reference is selected by control bits s1ync2 - s1ync0 (bits 2-0 in register 024h) for scout1 and control bits s2ync2 - s2ync0 (bits 2-0 in reg- ister 025h) for scout2. 2. the actual clock period and high or low times are a function of the selected clock rclkn. 3. a fault detected (los or rscann lead active if enabled by control bit exlos (bit 3 in register x+00h) set to a 1) by the particular channel selected for the reference clock will cause scout1 to stay low if control bit s1yncen (bit 5 in register 024h) is set to 1. a fault detected (los or rscann lead active if enabled by control bit exlos set to a 1) by the particular channel selected for the reference clock will cause scout2 to stay low if control bit s2yncen (bit 5 in register 025h) is set to 1. the output only goes to tristate only if control bit s1ctri or s2ctri is set to 1. 4. for a nrz setting of the line decoder by control bit rail (bit 7 in register x+00h) set to 0 and control bit rxcp (bit 5 in register x+00h) set to 0 the 8 khz pulse on scout1 and scout2 is coincident with the first bit of a frame if control bit synlf (bit 6 in register 00ch) is set to a 1; for rxcp set to 1 the pulse is coincident with the center of the last bit of a frame. for ami or hdb3 mode (rail set to 1) the pulse is coincident with the fourth bit of a frame for rxcp set to 0; for rxcp set to 1 the pulse is coincident with the center of the third bit of a frame. this feature works in framed modes only. 5. the above measurements are with the dejitter buffers disabled. a delay of 29.5 clock cycles is added with the dejit- ter buffers enabled. parameter (see note 2) symbol min typ max unit scout1,2 clock period when control bit s18khz, s28khz = 0 t cyc(1) 465 488.3 ns scout1,2 high time when control bit s18khz, s28khz = 0 t pwh(1) 0.5 x t cyc(1) ns scout1,2 low time when control bit s18khz, s28khz = 0 t pwl(1) 0.5 x t cyc(1) ns scout1,2 clock period when control bit s18khz, s28khz = 1 t cyc(2) 256 x t cyc(1) ns scout1,2 high time when control bit s18khz, s28khz = 1 t pwh(2) 465 488.3 ns scout2 (output) t pwl(1) t pwh(1) t cyc(1) scout2 (output) t cyc(2) t pwh(2) (control bit s18khz,,s28khz = 0) (control bit s18khz,,s28khz = 1) scout1 scout1 note 3 note 3 first frame bit for decoder = nrz rposn/rnrzn see note 4 note: n=1 - 8 (control bit rxcp = 0) - 75 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 34. auxiliary port receive timing (clock slave) note: when control bit radirsel (bit 0) in register 037h is set to a 0, raclk and rasync are inputs. parameter symbol min typ max unit raclk clock period t cyc 465 488.3 ns raclk low time t pwl 233 0.5 x t cyc ns raclk high time t pwh 233 0.5 x t cyc ns radat delay after raclk t d 5.0 15 28 ns rasync setup time to raclk t su 10 ns rasync hold time after raclk t h 15 ns rasync period t fcyc 465 256 x t cyc ns raclk radat t cyc rasync t pwl (input) (output) (input) t pwh t su t h t d bit 256 bit 1 (first bit of time slot 0) bit 2 t fcyc - 76 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 35. auxiliary port receive timing (clock master) note: when control bit radirsel (bit 0) in register 037h is set to a 1, raclk and rasync are outputs. control bit racksel (bit 1) in register 037h when set to 1 selects bposc as the source of raclk and rasync. when racksel is set to 0, control bits s1ync2 - s1ync0 (bits 2-0) in register 024h select the receive line clock rclkn as the source of raclk and rasync. parameter symbol min typ max unit raclk clock period t cyc 435 488.3 ns raclk low time t pwl 180 0.5 x t cyc ns raclk high time t pwh 180 0.5 x t cyc ns radat delay after raclk t d(1) 2.0 8.0 17 ns rasync delay after raclk t d(2) 1.0 10 14 ns rasync pulse width t pw 435 488.3 ns rasync period t fcyc 256 x t cyc ns raclk radat t d(1) t cyc rasync bit 256 bit 1 (first bit of time slot 0) t pwl bit 2 (output) (output) (output) t pwh t pw t d(2) t fcyc - 77 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 36. auxiliary port transmit timing (clock slave) note: when control bit tadirsel (bit 2) in register 037h is set to a 0, taclk and tasync are inputs. parameter symbol min typ max unit taclk clock period t cyc 435 488.3 ns tac l k l o w t i m e t pwl 180 0.5 x t cyc ns taclk high time t pwh 180 0.5 x t cyc ns tadatn setup time to taclk t su(1) 12 ns tadatn hold time after taclk t h(1) 12 ns tasync setup time to taclk t su(2) 12 ns tasync hold time after taclk t h(2) 12 ns tasync period t fcyc 256 x t cyc ns taclk tadatn (input) t cyc tasync bit 256 bit 1 (first bit of time slot 0) t pwl bit 2 (input) (input) t pwh note: n=1 - 8 t su(2) t h(2) t su(1) t h(1) t fcyc - 78 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 37. auxiliary port transmit timing (clock master) note: when control bit tadirsel (bit 2) in register 037h is set to a 1, taclk and tasync are outputs. control bit tacksel (bit 3) in register 037h when set to 1 selects bposc as the source of taclk and tasync. when tacksel is set to 0, control bits s1ync2 - s1ync0 (bits 2-0) in register 024h select the receive line clock rclkn as the source of taclk and tasync. parameter symbol min typ max unit taclk clock period t cyc 435 488.3 ns taclk low time t pwl 180 0.5 x t cyc ns taclk high time t pwh 180 0.5 x t cyc ns tadat setup time to taclk t su(1) 12 ns tadat hold time after taclk t h(1) 12 ns tasync delay after taclk t d(1) 1.0 10 14 ns tasync pulse width t pw 435 488.3 ns tasync period t fcyc 256 x t cyc ns taclk tadat (input) t su(1) t cyc tasync bit 256 bit 1 (first bit of time slot 0) t pwl bit 2 (output) (output) t pwh t pw t d(1) t fcyc t h(1) - 79 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers operation the following sections detail the internal operation of the e1fx8. line interface selection each of the eight framers in the e1fx8 can be programmed to provide either a dual unipolar interface or a nrz interface. the dual unipolar interface is selected when a 1 is written into control bit rail (bit 7) in the framer configuration register located at address x+00h in the memory map. the x stands for the framer selected, and will be equal to the value shown in the per channel control and status indication registers section (x= 0200h for framer 1, x=0400h for framer 2, etc.). the hdb3 line or ami coder/decoder (codec) feature can be selected for the dual unipolar interface. the hdb3 codec is selected by writing a 1 to control bit be (bit 6) in the framer configuration register x+00h. a 0 will select an ami codec. the hdb3 stands for high density bipolar of order 3, which is described in itu-t g.703 - 1993 annex a. the clock polarity of the input and output line clocks is selectable by writing the sense required to control bits txcp (bit 3) in the framer configuration register x+05h and rxcp (bit 5) in the framer configuration register x+00h. when a framer is configured for the dual unipolar mode, the line signal is monitored for loss of signal (los). los is detected if no transitions are present on either rposn or rnegn as defined by control bits losi7-losi0 in register 02ah, and enlosi in register 02bh. the binary value written to losi7-losi0 deter- mines the number of consecutive missing pulses to detect los. when enlosi is set to 1, the binary value in losi7-losi0 is multiplied by 16. to comply with itu-t g.775 set enlosi to a 0 and losi7-losi0 may be set in the range of 0ah to ffh (10 to 255 pulse periods). for isdn applications itu-t i.431 or ets 300 233 com- pliance may be met by setting enlosi to a 1 and losi7-losi0 to 7fh (2048 pulse positions or 1.0 millisec- ond of no pulses). recovery occurs when a ones density as determined by control bits ond5-ond0 in register 02bh is met; the binary value of pulses in the interval set by losi7-losi0 must equal or exceed the value writ- ten to ond5-ond0. a loss of signal alarm will be indicated in status bit los (bit 7) in register x+10h. an associated mask bit mlos, a latched event bit llos, a performance value plos and a fault value flos are all bit 7 of registers x+14h, x+11h, x+12h and x+13h respectively. the connections between a e1fx8 framer and external line interface transceivers are shown in figure 38 below for dual unipolar mode. figure 38. line interface for dual unipolar mode a coding violation counting function is provided in ami and hdb3 modes. control bit enzc (bit 1) in register x+00h when set to a 1 counts a string of 4 zeros as a coding violation in hdb3 mode and 16 zeros as a coding violation in ami mode. a 16 bit coding violation counter cv15- cv0 is located at x+f8h and x+f7h in the memory map with overflow bit cvo (bit 7) in register x+f9h. a shadow register of the counter and overflow bit lcv15-lcv0 and lcvo are located at x+f5h, x+f4h and x+f6h. line interface transceiver e1fx8 receive rposn rnegn rclkn tposn tnegn tclkn lcsn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 8) other tr a n s c e i v e r s for channel n - 80 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the nrz interface is selected when a 0 is written into control bit rail (bit 7) in register x+00h. the clock polarity of the line input and output clocks is selectable by writing the sense required to control bits txcp (bit 3) in the framer configuration register x+05h and rxcp (bit 5) in the framer configuration register x+00h. options are provided for inverting the polarity of the transmit and receive data leads. a 1 written to control bit txnrz (bit 2) in register x+05h inverts the polarity of the transmit data signal, tnrzn, while a 1 written to control bit rxnrz (bit 4) in register x+00h inverts the polarity of the receive data signal rnrzn. in nrz mode, the rnegn lead also designated rscann may be used to input an external indication of coding violations, loss of signal, or a fast sync pulse for testing purposes. the following table summarizes the line interface options (where x=don?t care). external coding violations are counted in the same 16-bit performance counter used in dual unipolar mode when control bit exlos (bit 3) in register x+00h is a 0. coding violations are counted when the input on rscann is high for active edges of the line clock rclkn. when control bit rxfs (bit 1) in register x+1ff is a 1, the rscann lead is used for inputting a receive fast sync pulse. a single rclkn clock period high pulse will force the framer to interpret the next bit on rnrzn as the first bit of a multiframe. proper time slot 0 fas and nfas patterns are necessary to remain in sync. when control bit exlos is set to a 1, rscann may be used to input loss of signal or loss of clock from an external detector. the active level is set by control bit elosn (bit 2) in register x+00h. when control bit elosn is a 1, the input sense is active low (i.e. active low is a loss of signal indication). when the control bit is a 0, the alarm sense is active high. the following is a summary of the actions taken by the two control bits (where x=don?t care). in the dual unipolar mode, a single coding violation can be transmitted to verify receiving equipment operation. setting control bit bpve (bit 5) in register x+106h to a 1 will cause a single coding violation to be generated. bpve must be set to a 0 before another coding violation can be sent. in hdb3 mode a coding violation may mimic a zero substitution and not be recorded as an error by the receiving equipment; e.g. a ?1001? which would normally be sent as a ?b00b? could be triggered to become a ?b00v? (validly decoded as 0000 not as a code violation) if control bit bpve were set to a 1 in the middle of transmitting ?b00b?. ?b? is a normal bipolar pulse (alternate polarity to the previous pulse) and ?v? is a bipolar violation (same polarity as the previous pulse). rail be exlos rxfs e1 receive line input action 0 x 1 0 nrz interface selected. rnegn lead may be used to input an external los. 0 x 0 1 nrz interface selected. rnegn lead may be used to input a nx2.0 ms sync pulse. 0 x 0 0 nrz interface selected. rnegn lead may be used to input a bpv count. 0 x 1 1 not used. 1 0 x x rail interface selected. ami line coding selected. 1 1 x x rail interface selected. hdb3 line coding selected. exlos elosn e1 receive line input action 0 x nrz interface selected. the rnegn lead may be used to input an external bipolar coding violation. external los alarm indication is disabled. 1 0 nrz interface selected. the rnegn lead may be used to input an external loss of signal indication. the input state to indicate an external loss of signal is active high. access to the counter via the external lead is disabled. 1 1 nrz interface selected. the rnegn lead may be used to input an external loss of signal indication. the input state to indicate an external loss of signal is active low. access to the counter via the external lead is disabled. - 81 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers in the transmit direction, when the nrz mode is selected, the tnegn lead becomes a tdrvn lead. the lead may be used to output a fast sync pulse on a frame or superframe basis, or it may be used as a general pur- pose output lead. when control bit tdfme (bit 7) in register x+07h is a 1, a fast sync output pulse is provided on this lead. the control bit tlmf (bit 5) in the same register determines if the output pulse is every 125 micro- seconds or occurs at the superframe rate of every 1.5 or 3 milliseconds. when control bit tdfme is a 0, the tdrvn lead can be used as a general purpose output lead whose level is determined by control bit txdrv (bit 6) in the same register. the following table summarizes the transmit options (where x=don?t care). a typical interface between a framer in the e1fx8 and an external line transceiver is shown in figure 39 below for the nrz mode. figure 39. line interface for nrz mode receive dejitter buffer a 64-bit dejitter buffer is provided to remove line, de-mapping or de-multiplexing jitter when an external dejitter buffer is not provided by an liu or other device and when receive slip buffer usage is not practical for a given application. both rposn/rnrzn and rnegn are dejittered using a digitally controlled oscillator and 64-bit fifo. the transfer function is that of a single pole low pass filter with the pole at approximately 10 hz; wander passes through but jitter is attenuated. a remote loopback (control bits rlp (bit 5) and llp (bit 7) in register x+107h are set to 1 and 0 respectively) also goes through the dejitter buffer and clock reference selections are taken from the dejittered clock outputs when it is enabled. the on board dpll runs at 64512 khz to operate the dejitter buffers. the dpll signal may be input on lead dpllref and the dpll may be disabled if control bit disecksyn (bit 4) in register 0feh is set to a 1. when disecksyn is set to a 0, lead dpllref is an out- put. each dejitter buffer may be recentered or bypassed by per framer control bits recenter and bypass respectively (bits 1 and 0) in register x+161h. setting recenter to a 1 will recenter the dejitter buffer once. setting bypass to a 0 will cause the dejitter buffer to be bypassed. to completely shut down the dejitter buffer to conserve power, set bypass to a 0, disecksyn to a 1 and resecksyn to a 1 simultaneously. the bypass set to 0 disables the dejitter buffer and clock synthesis, disecksyn set to a 1 keeps the high fre- quency generator in power down and resecksyn set to a 1 keeps the counter in the high frequency block rail tdfme tlmf action 1 x x rail interface, b8zs or ami line coding 0 0 x nrz interface. control bit txdrv determines the state of the tdrvn lead. 0 1 0 nrz interface. the tdrvn lead provides a one clock cycle wide framing pulse that occurs at a 125 s rate except in transparent mode (control bit ttfm is a 1). 0 1 1 nrz interface. the tdrvn lead provides a one clock cycle wide framing pulse that occurs at a 2.0 ms rate except in transparent mode (control bit ttfm is a 1). e1fx8 receive rnrzn rclkn tnrzn tdrvn tclkn lcsn rscann lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 8) other transceivers line interface transceiver for channel n - 82 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers reset. each dejitter buffer can be made to recenter automatically on overflow or underflow or to pass the jitter through if the overflow or underflow limits are reached. control bit attnlm (bit 2) in register x+161h when set to a 1 allows the dejitter buffer to automatically recenter; this will cause a loss or repetition of data. since the dejitter buffer has much more head room than required by the standards, the input signal needs to be substan- tially out of specification to cause an underflow or overflow. when attnlm is set to a 0, no data is lost but the jitter present on the input is passed through until the dejitter buffer can recover. the requirements for the dejitter buffer are listed below: the jitter transfer characteristics of the e1fx8 with the dejitter buffer enabled are shown in figure 40. the jitter transfer gain is well below the -19.5 db for frequencies above 400 hz (meets requirements of g.735 and g.736). dejitter buffer specification format: single or dual rail depth: 64 bits (x2 wide) total normal location: between the rposn and rnegn inputs and the codec. test location: when enabled, it is in the remote loopback path internal connections for clocks: when enabled its output clock is used for scout1,2 (s1extb, s1sint = 11), monitor output, rtclkn (rxcke = 1) and tclkn (txc1, txc0 = 10) nominal frequency range: 2048 khz 50 ppm nominal output jitter with jitter free reference: <0.05 uip-p 20 hz to 100 khz (g.735/g.736) maximum output jitter with jitter free reference: 0.10 uip-p 20 hz to 100 khz (g.735/g.736) minimum jitter attenuation at 10 hz: 0 db to tolerance limit of g.823 minimum jitter attenuation at 400 hz: =20 db to tolerance limit of g.823 (g.735/g.736) minimum jitter tolerance (g.823 - 1993): 1.2 x10 -5 hz to 4.88 x10 -3 hz = 36.9 uip-p 0.01 hz to 1.667 hz = 18 uip-p 20 hz to 2.4 khz = 1.5 uip-p 18 khz to 100 khz = 0.2 uip-p curves between ranges is 20 db/decade roll off. overflow or underflow operation: when control bit attnlm is set to a 0 and the dejitter buffer reaches limit of storage, jitter is passed through rather than dropping data. when control bit attnlm is set to a 1 and the dejitter buffer reaches limit of storage, the dejitter buffer is recen- tered causing a loss or repetition of data. - 83 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 40. e1fx8 jitter transfer characteristics 0.5 log scale measured itu-t rec.g.735/ g.736limit db scale frequency -10.0 jitter transfer gain (db) test conditions: v dd = 3.3 v, t a = 25 c -20.0 -30.0 10 hz 100 hz 1 khz 100 khz 1 mhz 10 khz -19.5 0.0 frequency jitter transfer gain frequency jitter transfer gain 15.0 hz -4.7 db 2.4 khz -30.0 db 40.0 hz -11.4 db 4.8 khz -30.0 db 200.0 hz -21.3 db 18.0 khz -30.0 db 464.0 hz -22.0 db 36.0 khz -30.0 db 600.0 hz -25.0 db 72.0 khz -30.0 db 800.0 hz -27.2 db 100.0 khz -30.0 db note: narrow isolated spikes occur at 464 hz and 600 hz, magnitude as shown, but well below the requirements of the itu-t specifications. 40 hz 400 hz 20 db/decade -22.0 464 hz * -25.0 * 600 hz - 84 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers line interface control this interface permits the microprocessor to have complete control of the eight external line interface trans- ceivers through the e1fx8. this interface is selected by setting global control bit espbmon (bit 5) in register 01dh to a 0 for the 208-lead package; this interface is always available in the 256-lead package. the line inter- face control leads are common to all eight framers and comprise a data input lead (lsdi), a data output lead (lsdo), and a clock output lead (lsclk). the clock signal lsclk is derived from the signal at the bposc lead; it is the same frequency as the signal applied to the bposc lead. individual chip select leads (lcsn ) are used between the e1fx8 and the external transceivers to determine which of the eight external transceivers is to be accessed through the e1fx8. typical interfaces between the e1fx8 and external line interface transceiv- ers using the line interface control leads are shown in figure 38 and 39, for the dual unipolar and nrz interface modes, respectively. data to be written to the external transceiver is formatted as a two-byte message. the first byte is an address/command byte and the second byte contains the data to be written or read. figure 41 illustrates the message and control formats associated with the transceiver serial i/o timing. figure 41. transceiver serial i/o timing the format of the address/command byte depends upon the external transceiver being controlled. please refer to the transceiver's data sheet for the command/data formats. the interface for controlling the external trans- ceiver operates in the following way. the external transceiver selection (via lcsn ) is determined by the value written to three bits e1chs2, e1chs1, and e1chs0 (bits 2 - 0) in register 01dh. for example, a 000 value selects the transceiver for framer 1 while a 111 value selects the transceiver for framer 8. the microprocessor writes the command byte to lcb7-lcb0 in the line interface control register 01eh. this is followed by writing the data byte to ldo7-ldo0 in line interface control register 01fh. the serial message is sent on lsdo when a 1 is written to replace the 0 in the esp bit (bit 6) in register 01dh. the esp bit must be first written with a 0, followed by a 1, before another transfer can take place between the e1fx8 and the external transceiver selected. broadcast capability to all transceivers is enabled when the control bit bdcst (bit 7) in register 01dh is written with a 1. for a read operation, the read command is sent on lead lsdo as described above. eight clock cycles later, the selected transceiver will respond by sending serial data on the lsdi input lead. the data is shifted in lsb first to ldi7-ldi0 in the serial port data input register 020h. lcsn lsclk lsdo lsdi addrd0d1d2d3d4d5 d6 d7 r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7 - 85 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers monitor mode the monitor mode interface permits the e1fx8 to provide an external receive or transmit nrz signal from one of the framers to an external device. this interface is selected by setting global control bit espbmon (bit 5) in register 01dh to a 1 for the 208-lead package; this interface is always available in the 256-lead package. please note that the leads for this mode are shared with the line control interface in the 208-lead package, and if the monitor mode is selected, these leads cannot be used to provide a serial interface between the external transceivers and the e1fx8. in addition, a 0 must be written into the montr control bit (bit 5) in the global configuration register 022h to enable the monitor mode interface output leads. a 1 written into montr control bit causes these data, frame, and clock leads to be tristated, permitting multiple e1fx8 devices to share an external line driver. a 1 written to control bit monrx (bit 7) in register 022h selects the receive side, while a 0 selects the transmit side. for the receive side the data stream may be monitored before or after the receive framer selected by con- trol bit monrf (bit 6) in register 022h. the framer to be monitored is selected by the value written into the mfr2, mfr1 and mfr0 control bits (bits 2-0) in register 022h. for example, a value of 000 selects framer 1, and a value of 111 selects framer 8. the selected framer nrz signal is provided on output lead mondat and the frame pulse is provided on output lead monfrm. the nrz receive or transmit data is clocked out on rising edges of the monclk clock lead signal. if los, ais or oof is detected while monitoring the receive side (i.e., while control bit monrx is set to 1), the frame pulse will cease to be present on lead monfrm. however, detection of los, ais or oof will not affect the frame pulse output on lead monfrm while monitoring the transmit side (i.e., while monrx is set to 0). note: x=don?t care monrx monrf montr action x x 1 the monitor data lead (mondat), clock lead (monclk), and framing pulse lead (monfrm) are tristated to allow other e1fx8s to share a bus. 0 x 0 transmit monitoring selected. framer selected is determined by control bits mfr2-mfr0, where 000 is framer 1. the monitor data lead (mondat), clock lead (monclk), and framing pulse lead (monfrm) are provided as outputs. 1 0 0 receive monitoring selected. data stream monitored before the input to the receive framer. the framer whose input is selected is determined by control bits mfr2-mfr0, where 000 is framer 1. the monitor data lead (mondat), clock lead (monclk), and framing pulse lead (monfrm) are provided as outputs. 1 1 0 receive monitoring selected. data stream monitored after the receive framer. the framer whose output is selected is deter- mined by control bits mfr2-mfr0, where 000 is framer 1. the monitor data lead (mondat), clock lead (monclk), and fram- ing pulse lead (monfrm) are provided as outputs. - 86 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers system interface the system interface connects each of the eight framers within the e1fx8 to and from the system. the system interface is selected by the conf0 and conf1 input leads and control bit dintf (bit 1) in global register 00bh according to the table shown below (where x=don?t care). for the transmission and data modes each framer has separate transmit and receive interfaces that are referred to as receive and transmit highways. each highway consists of a serial data bus (i.e., data highway) rtdatn/ttdatn, a serial signaling bus (i.e., signaling highway) rtsign/ttsign, a clock rtclkn/ttclkn, a separate gapped clock or marker output for transmit and receive rtauxn/ttauxn, a serial auxiliary transmit data input ttaixn for fractional e1, and frame synchronization signal rtfrmn/ttfrmn. in the receive direc- tion, clock and frame synchronization are outputs or inputs (slip buffer required if the receive clock and frame are inputs). for the mvip mode, each framer has separate transmit and receive interfaces that are referred to as receive and transmit highways. each highway consists of a serial data bus (i.e., data highway) rtdatn/ttdatn, a serial signaling bus (i.e., signaling highway) rtsign/ttsign, a clock rtclkn/ttclkn, and a synchronization signal rtfrmn/ttfrmn. in the receive direction, clock and frame synchronization are inputs (slip buffer required). for the h-mvip and h.100 modes, four framers (i.e., 1-4 and 5-8) share transmit and receive interfaces that are referred to as receive and transmit highways. each highway consists of a byte- interleaved serial data bus (i.e., data highway) rtdat1,5/ttdat1,5, a byte-interleaved serial signaling bus (i.e., signaling highway) rtsig1,5/ttsig1,5, a clock rtclk1,5/ttclk1,5, and a synchronization signal rtfrm1,5/ttfrm1,5. in the receive direction, clock and frame synchronization are inputs (slip buffer required). internally, each data bus is connected to a two-frame slip buffer per framer, and each signaling bus is connected to a 120-bit signaling buffer per framer. two additional active receive signaling buffers are also pro- vided per framer for signaling debounce. please note that control bits are provided which enable the slip buff- ers to be bypassed when the transmission or data modes are selected. for the mvip, h-mvip and h.100 modes, the receive and transmit slip buffers must be enabled by setting control bits rxsbe (bit 5) in register x+11bh to a 1, and txsbe (bit 5) in register x+11ch to a 1. the system interface has a wide variety of options, not all of which are available in all interface modes. the table below lists the options available in each mode. unless restricted by a lead signal, all features are avail- able in all modes in the 208-lead package rtauxn and rtsign share a lead as do ttauxn and ttsign. control bit fe1m (bit 4) in register x+07h when set to a 1 selects rtauxn and ttauxn; when set to a 0 rtsign and ttsign is selected. dintf conf1 conf0 configuration selected 0 low low transmission interface 1 low low data interface x low high mvip interface 0highlowh-mvip 1 high low h-mvip with h.100 frame pulse width option x high high not used function transmission mode data mode mvip mode h-mvip/h.100 no. of time slots on r/ttdatn 32 32 32 128 (r/ttdat1,5) rtclkn 2.048 mhz in & out 2.048 mhz in & out 2.048 mhz in only 16.384 mhz in only ttclkn 2.048 mhz in only 2.048 mhz in only 2.048 mhz in only 16.384 mhz in only rtfrmn 2.0 ms in & out 125 s in & out 125 s in 125 s in - 87 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmission mode the transmission mode is enabled when a low is placed on both the conf0 and conf1 leads and control bit dintf (bit 1) in register 00bh is set to 0. transmit highway with fractional e1 support when the transmission mode is selected, the transmit highway carries information from the system to the e1fx8 for each framer. the highway is subdivided into two time division multiplexed buses, one for data (ttdatn), and the other one for signaling, alarms and selected bits that may be multiplexed into time slot 0 (ttsign). the n in the ttdatn and ttsign signals represents one of the eight framers. the two buses are synchronous with respect to the highway clock (ttclkn), which has a clock rate of 2048 khz. the data high- way is a single bit-serial bus organized into 256-bit groups called frames, with the bits in each group numbered 1 through 256. each frame consists of 32 time slots numbered from 0 to 31, as shown in figure 42. time slot 0 carries the frame synchronization pattern, multiframe pattern for the crc-4 multiframe option which uses the international bits, rai bits and sa4 through sa8 national bits. also note that 16 frames form a multiframe for the crc-4 option, with the beginning of each multiframe identified by an active high synchronization pulse (ttfrmn), one (ttclkn) clock cycle wide, which occurs every 2 ms, normally at the end of frame 16. each multiframe carries two sub-multiframes. each sub-multiframe carries a crc-4 calculated over the previous sub-multiframe. every second sub-multiframe carries two far end error bits (e-bits) for the current and the pre- vious sub-multiframes. the position of the ttfrmn pulse is programmable to any bit position within the data bus frame using control bits tfrm7-tfrm0 in register 02fh. the synchronization pulse is aligned to bit 8 in time slot 31 in frame 15 when a value of 00h is written into this register. data from the data highway may be enabled on a per time slot basis for transmission to the e1 line. control bits tde1 through tde31 in control registers x+e4h, x+e5h, x+e6h and x+e7h when set to a 1 enable the time slot data to the line for the selected time slots. the signaling bus (ttsign) is also divided into 256-bit frames. each signaling frame consists of 256-bits of signaling and alarm information for the 30 telephone channels, numbered from 1 to 30, that are carried on the data bus occupying time slots 1 through 15 and 17 through 31. the first time slot (time slot 0) in the signaling highway is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the posi- tions of the time slot 0 bits in this frame are the same as found in time slot 0 of the e1 frame format. it is not ttfrmn 2.0 ms in 125 s in 125 s in 125 s in r/ttsign 8 bits/125 s 120 bits/125 s 120 bits/125 s 480 bits/125 s r/tauxn 64 kbit/s gapped clock or marker 64 kbit/s gapped clock or marker not available; forced to zero not available; forced to zero no. of time slots from ttaixn up to 31 up to 31 not available not available alarms on r/ttsign ais & rai in/out not available not available not available time slot 0 national and international bits in & out on r/ttsign & r/ttdatn in & out on r/ttsign & r/ttdatn in & out on r/ttsign & r/ttdatn in & out on r/ttsign & r/ttdatn unframed mode yes; with or without slip buffering yes; with or without slip buffering not available not available function transmission mode data mode mvip mode h-mvip/h.100 - 88 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers required that the time slot 0 bits from the signaling highway carry the frame alignment pattern in fas frames or have bit 2 in nfas frames set to a 1. as an option, the international bits and the national bits may be sourced from ttsign; when control bit bnal (bit 5) in register x+122h is set to a 1, control bits tsa4s through tsa8s (bits 4-0) in register x+e3h set to a 1 select the national bits to be sourced from time slot 0 of ttsign. control bit tsis (bit 7) in register x+e3h when set to a 1 selects the international bits to be sourced from time slot 0 of ttsign if control bits crcmd1,0 equal 01 which corresponds to crc-4 disabled. time slot 1 in the signaling highway carries the channel associated signaling (cas) multiframe format. like time slot 0 multiframe, this multiframe is repeated every 16 frames. the multiframe alignment pattern (0000), and the spare and multiframe alarm bits (x0, y, x1, x2) occur in frame 0, followed by the abcd signaling bits for telephone channels 1 through 30 (starting with telephone channels 1 and 16 in frame 1 and ending with telephone channels 15 and 30 in frame 15). the remaining bits are marked ?a? in time slots 2 through 31 and carry an ais indication, when set to 1, on the system side. status bit tabit (bit 5) in register x+17h indicates the state of these a-bits. if control bit extais (bit 5) in register x+06h is set to a 1 and the a-bits on ttsign are set to 1, an unframed all ones (ais) will be transmitted by the e1fx8. likewise, if control bit extrai (bit 4) in register x+06h is set to a 1 and the r-bit (bit 3) in time slot 0 of odd frames is set to a 1 indicating a system side rai, the a-bit (bit 3) of the transmitted time slot 0 in nfas frames will be set to a 1 indicating rai. the status of the r-bit on the signaling highway is indicated in status bit tybit (bit 4) in register x+17h. it is not necessary to place a multiframe alignment pattern in time slot 1 frame 1. time slot 16 spare bits may be sourced from ttsign by setting control bits tx2s, tx1s and tx0s (bits 2-0) in register x+e2h to 1 for each spare bit selected. in figure 42 below the s1 through s8 bits represent the abcd signaling states associated with each pair of telephone channels. the e1fx8 inserts the signaling bits from the signaling highway into the transmitted time slot 16 if enabled by control bits tse1 through tse30 in registers x+ech, x+edh, x+eeh and x+efh. figure 40 shows the operation of the gapped clock or marker output ttauxn as well as the auxiliary input ttaixn. ttauxn is shown with a gapped clock output for time slot 1. the 32 control bit pairs tc1cc/tc0cc in registers x+112h through x+118h determine the source of each transmitted time slot (c = 0 - 31); it can come from the ttdatn, ttaixn, the idle code insertion register (x+119h) or a digital milliwatt generator. control bit tchmk (bits 7) in register x+110h controls the ttauxn signal. tchmk set to 1 selects a channel marker (ttauxn high for 8 clock periods of selected time slot). control bit ulaw (bit 2) in register x+06h selects the coding law used to generate the digital milliwatt. the table below shows the options described (where x= don?t care). these features are generally available in all system interface modes unless the lead is not supported in that mode. for example, if tc1cc and tc0cc are set to 01, fractional e1 functions are available, except that gapped clocks on ttauxn or inputs from ttaixn are not available in mvip or h-mvip/h.100 modes. tc1cc tc0cc tchmk ulaw action for the selected time slot 0 0 x x normal operation. the time slot (c= 1 - 31) is transmitted intact from the data highway, ttdatn. the ttaixn lead is disabled. 0 1 0 x fractional e1 service. 64 kbit/s gapped clock provided on the ttauxn lead, and data from ttaixn lead is multiplexed into transmit bit stream. 0 1 1 x fractional e1 service. channel marker provided on the ttauxn lead, and data from ttaixn lead is multiplexed into transmit bit stream. 1 0 x x insert microprocessor-written idle code value from register x+119h. no gapped clock or channel marker generation on the ttauxn lead. the ttaixn lead is disabled. 1 1 x 0 a-law digital milliwatt generated for the time slot selected. no gapped clock or marker channel generation on ttauxn lead. the ttaixn lead is disabled. 1 1 x 1 mu-law digital milliwatt generated for the time slot selected. no gapped clock or marker channel generation on ttauxn lead. the ttaixn lead is disabled. - 89 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 42. transmit highway - transmission mode ttfrmn ttclkn/ ttdatn/ ttsign 2 ms (multiframe) time slot 31 8 bits per channel time slot 2 time slot 1 time slot 0 fas/nfas (for si/sa insertion, rai insert) s 2 s 1 s 3 s 4 s 5 s 6 s 7 s 8 aa a aaaaa a aa aa aaaa a aaaa aa frame 15 frame 2 frame 1 frame 0 one frame (256 bits) si x r sa4 sa5 sa6 sa7 sa8 si x x x x x x x notes: si = international bits r = remote alarm indication (rai) san = national bits (n = 4-8) xb = spare bits (b = 0-2) y = multiframe alarm ac bc cc dc = abcd signal bits for channel c (1-30) 181818 18 125 s a = alarm bits (ais) even frames odd frames bit, known as ts0 a-bit ttaixn ttauxn frame rtsig; s1 - s8 0 0, 0, 0, 0, x0, y, x1, x2, 1 a1, b1, c1, d1, a16, b16, c16, d16 2 a2, b2, c2, d2, a17, b17, c17, d17 3 a3, b3, c3, d3, a18, b18, c18, d18 4 a4, b4, c4, d4, a19, b19, c19, d19 5 a5, b5, c5, d5, a20, b20, c20, d20 6 a6, b6, c6, d6, a21, b21, c21, d21 7 a7, b7, c7, d7, a22, b22, c22, d22 8 a8, b8, c8, d8, a23, b23, c23, d23 9 a9, b9, c9, d9, a24, b24, c24, d24 10 a10, b10, c10, d10, a25, b25, c25, d25 11 a11, b11, c11, d11, a26, b26, c26, d26 12 a12, b12, c12, d12, a27, b27, c27, d27 13 a13, b13, c13, d13, a28, b28, c28, d28 14 a14, b14, c14, d14, a29, b29, c29, d29 15 a15, b15, c15, d15, a30, b30, c30, d30 gapped clock ttauxn is shown for pulse width = 488 ns time slot 1 (the marker is a single 8 bit wide pulse) comes out one clock cycle earlier relative to ttdatn in the transmit direction. - 90 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive highway with fractional e1 support in the transmission mode, the receive highway for each framer carries information from the e1fx8 to the system. like the transmit path, the receive highway is also subdivided into two time division multiplexed buses, one for data (rtdatn), and one for signaling and alarms (rtsign), where n represents one of the eight framers. the two buses are synchronous with the highway clock (rtclkn), which has a clock rate of 2048 khz. the clock (rtclkn) is either an output to the system or an input from the system. the system clock (rtclkn) or the line clock (rclkn) may be the input clock source for the slip buffer when it is enabled. usually the system clock (rtclkn) is used. the e1fx8 must be set to source the clock (rtclkn) as an output when the slip buffer is bypassed. the receive slip buffer for a framer is disabled when a 0 is written to the rxsbe bit (bit 5) in the register x+11bh. the clock source selection is determined by the rxcke bit (bit 7) in register x+11bh. a 0 written into this bit position selects the system clock (rtclkn) as the source clock. in addition to controlling the source of the clock, control bit rxcke also controls the source of the synchronization pulse. the data bus is a single bit-serial bus organized into 256-bit groups called frames, as shown in figure 43, with the bits in each group numbered 1 through 256. each frame consists of 32 time slots numbered from 0 to 31, as shown in figure 43. time slot 0 carries the frame synchronization pattern, multiframe pattern for the crc-4 multiframe option which uses the international bits, rai bit and sa4 through sa8 national bits. also note that 16 frames form a multiframe for the crc-4 option, with the beginning of each multiframe identified by an active high synchronization pulse (rtfrmn), one (rtclkn) clock cycle wide, which occurs every 2 ms, normally at the end of frame 16. each multiframe carries two sub- multiframes. each sub-multiframe carries a crc-4 calculated over the previous sub-multiframe. every second sub-multiframe carries two far end error bits (e-bits) for the current and the previous sub-multiframes. the position of the rtfrmn pulse is programmable to any bit position within the data bus frame using control bits rfrm7-rfrm0 in register 02eh. the synchronization pulse is aligned to bit 8 in time slot 31 in frame 15 when a value of 00h is written into this register. data from the e1 line may be enabled on a per time slot basis for insertion on the data highway. control bits rde1 through rde31 in control registers x+3ch, x+3dh, x+3eh and x+3fh when set to a 1 enable the time slot data to rtdatn for the selected time slots. the signaling bus (rtsign) is also divided into 256-bit frames. each signaling frame consists of 256-bits of signaling and alarm information for the 30 telephone channels, numbered from 1 to 30, that are carried on the data bus occupying time slots 1 through 15 and 17 through 31. the first time slot (time slot 0) in the signaling highway is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the posi- tions of the time slot 0 bits in this frame are the same as found in time slot 0 of the e1 frame format. time slot 0 on rtsign is time slot 0 received from the e1 line but not subject to slip buffering. time slot 1 in the signaling highway carries the channel associated signaling (cas) multiframe format. like time slot 0 multiframe, this multiframe is repeated every 16 frames. time slot 16 multiframe alignment may or may not be aligned with time slot 0 multiframe on the e1 received signal. however, the internal signaling buffer provides alignment such that both multiframes are aligned on rtsign. the time slot 16 multiframe alignment pattern (0000), and the spare and multiframe alarm bits (x0, y, x1, x2) occur in frame 0, followed by the abcd signaling bits for telephone channels 1 through 30 (starting with telephone channels 1 and 16 in frame 1 and ending with telephone channels 15 and 30 in frame 15) as shown in figure 43 below. the remain- ing bits are marked ?a? in time slots 2 through 31 and carry an ais indication to the system side. the ?a? bits are set to 1 if the e1fx8 if control bit enabit (bit 4) in register x+02h is set to a 1 and either ais, oof or los is detected and enabled by control bits enais, enoof or enlos (bits 7-5) in register x+02h to set the ?a? bits. the ?a? bits may be forced to a 1 by setting control bit rtais (bit 2) in register x+02h to a 1 with control bit enabit set to a 1. ais (all ones) on rtdatn may also be forced under the same line conditions (enais, enoof and enlos plus the associated alarm or rtais is set to a 1) if control bit endbit (bit 3) in register x+02h is set to a 1. likewise, if control bit enrai (bit 1) in register x+02h is set to a 1 the ?r? bit (bit 3) in time slot 0 of odd frames is set to a 1 if a line rai, the a-bit (bit 3) of the received time slot 0 in nfas, has been set to a 1 for four or more consecutive times indicating rai. the ?r? bit on the signaling highway may also be forced to a 1 by setting control bit rtrai (bit 0) in register x+02h to a 1. in figure 43 below the s1 through s8 bits represent the abcd signaling states associated with each pair of telephone channels. the e1fx8 inserts - 91 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the signaling bits into the signaling highway from the received e1 time slot 16 after processing as described below if enabled by control bits rse1 through rse30 in registers x+e8h, x+e9h, x+eah and x+ebh. con- trol bits rx2s, rx1s and rx0s (bits 2-0) in register x+3ah when set to 1 enable the spare bits received on the e1 line time slot 16 to be placed on the signaling highway. control bits rsis (bit 7) and rsa4s- rsa8s in register x+3bh when set to 1 enable the international and national bits received on the e1 line to be placed on the signaling highway. figure 43 shows the operation of the gapped clock or marker output rtauxn. rtauxn is shown with a gapped clock output for time slot 1. the 32 control bits rfchc in registers x+1bh through x+1eh determine the sig- nal on rtauxn. control bit rchmk (bits 7) in register x+1ah controls the selected rtauxn signal. rchmk set to 1 selects a channel marker (rtauxn high for 8 clock periods of selected time slot). the table below shows the options described (where x=don?t care). data and signaling inversion to accommodate different system applications either the data (time slots) or the signaling (abcd) may be inverted to or from the system interface. alternate digit inversion (either odd or even bits) is also provided. this feature is available per e1. fas bits, nfas bits, spare bits, national bits and international bits and alarm bits are not inverted or altered by these control bits. control bits rdinv and rsinv (bits 7 and 6) in register x+04h, when set to 1, invert the time slot data to output lead rtdatn and the signaling bits to output lead rtsign, respectively. control bits tdinv and tsinv (bits 5 and 4) in register x+04h, when set to 1, invert the time slot data input from leads ttdatn and ttaixn and the signaling bits input from lead ttsign, respectively. control bit rdadi and tdadi (bits 3 and 2) in register x+04h invert the even bits of rtdatn and ttdatn respectively if set to 1 after inversion if any by rdinv or tdinv. the table below indicates the options (where x=don?t care). rfchc rchmk action for the selected time slot 0 x normal operation. channel not selected for fractional e1 service. rtauxn lead low. 1 0 fractional e1 service. 64 kbit/s gapped clock provided on the rtauxn lead. 1 1 fractional e1 service. 64 kbit/s channel marker provided on the rtauxn lead. rdinv rdadi rsinv tdinv tdadi tsinv action taken on highways 0 0 0 x x x received data, si bits, sa4 - sa8 bits, spare bits and signaling not inverted from line to rtdatn/rtsign. 0 0 1 x x x signaling bits only on rtsign inverted (frames 2 - 16). 1 0 0 x x x rtdatn inverted (time slots 1 through 31). 0 1 0 x x x even bits on rtdatn time slots 1 through 31 inverted. 1 1 0 x x x odd bits on rtdatn time slots 1 through 31 inverted. 1 0 1 x x x even bits on rtdatn time slots 1 through 31 inverted; signaling bits only on rtsign inverted (frames 2 - 16). 1 1 1 x x x odd bits on rtdatn time slots 1 through 31 inverted; signaling bits only on rtsign inverted (frames 2 - 16). x x x 0 0 0 data, signaling, si bits, sa4 - sa8 bits and spare bits selected to be transmitted as received on ttdatn/ttsign. x x x 0 0 1 signaling bits only from ttsign inverted (frames 2 - 16) x x x 1 0 0 ttdatn inverted (time slots 1 through 31). x x x 0 1 0 even bits from ttdatn time slots 1 through 31 inverted. x x x 1 1 0 odd bits from ttdatn time slots 1 through 31 inverted. x x x 1 0 1 even bits from ttdatn time slots 1 through 31 inverted; signaling bits only from ttsign inverted (frames 2 - 16). x x x 1 1 1 odd bits from ttdatn time slots 1 through 31 inverted; signaling bits only from ttsign inverted (frames 2 - 16). - 92 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 43. receive highway - transmission mode rtfrmn rtclkn rtdatn rtsign 2 ms (multiframe) time slot 31 8 bits per channel time slot 2 time slot 1 time slot 0 fas/nfas (for si/sa insertion, rai insert) s 2 s 1 s 3 s 4 s 5 s 6 s 7 s 8 aa a aaaaa a aa aa aaaa a aaaa aa frame 15 frame 2 frame 1 frame 0 one frame (256 bits) si 1 r sa4 sa5 sa6 sa7 sa8 si 0 0 1 1 0 1 1 notes: si = international bits r = remote alarm indication (rai) san = national bits (n = 4-8) xb = spare bits (b = 0-2) y = multiframe alarm ac bc cc dc = abcd signal bits for channel c (1-30) 181818 18 125 s a = alarm bits (ais) even frames odd frames bit, known as ts0 a-bit rtauxn frame rtsig; s1 - s8 0 0, 0, 0, 0, x0, y, x1, x2, 1 a1, b1, c1, d1, a16, b16, c16, d16 2 a2, b2, c2, d2, a17, b17, c17, d17 3 a3, b3, c3, d3, a18, b18, c18, d18 4 a4, b4, c4, d4, a19, b19, c19, d19 5 a5, b5, c5, d5, a20, b20, c20, d20 6 a6, b6, c6, d6, a21, b21, c21, d21 7 a7, b7, c7, d7, a22, b22, c22, d22 8 a8, b8, c8, d8, a23, b23, c23, d23 9 a9, b9, c9, d9, a24, b24, c24, d24 10 a10, b10, c10, d10, a25, b25, c25, d25 11 a11, b11, c11, d11, a26, b26, c26, d26 12 a12, b12, c12, d12, a27, b27, c27, d27 13 a13, b13, c13, d13, a28, b28, c28, d28 14 a14, b14, c14, d14, a29, b29, c29, d29 15 a15, b15, c15, d15, a30, b30, c30, d30 gapped clock rtauxn shown for time pulse) bit ts0fz (bit 5) reg. x+134h=0 pulse width = 488 ns slot 1 (the marker is a single 8 bit wide - 93 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers data mode the data mode is enabled when a low is placed on both the conf0 and conf1 leads and control bit dintf (bit 1) in register 00bh is set to 1. transmit highway with fractional e1 support when the data mode is selected, the transmit highway carries information from the system to the e1fx8 for each framer. the highway is subdivided into two time division multiplexed buses, one for data (ttdatn), and the other one for signaling (ttsign). the n in the ttdatn and ttsign signals represents one of the eight framers. the two buses are synchronous with respect to the highway clock (ttclkn), which has a clock rate of 2048 khz. the data highway is a single bit-serial bus organized into 256-bit groups called frames, with the bits in each group numbered 1 through 256. each frame consists of 32 time slots numbered from 0 to 31, as shown in figure 44. time slot 0 carries the frame synchronization pattern, multiframe pattern for the crc-4 multi- frame option which uses the international bits, rai bits and sa4 through sa8 national bits. also note that the beginning of each frame is identified by an active high synchronization pulse (ttfrmn), one (ttclkn) clock cycle wide, which occurs every 125 s, normally at the beginning of each frame. the position of the ttfrmn pulse is programmable to any bit position within the data bus frame using control bits tfrm7-tfrm0 in regis- ter 02fh. the synchronization pulse is aligned to bit 1 in time slot 0 in every frame when a value of 00h is written into this register. data from the data highway may be enabled on a per time slot basis for transmission to the e1 line. control bits tde1 through tde31 in control registers x+e4h, x+e5h, x+e6h and x+e7h when set to a 1 enable the time slot data to the line for the selected time slots. the signaling bus (ttsign) is also divided into 256-bit frames. each signaling frame consists of 120-bits of signaling information for the 30 telephone channels, numbered from 1 to 30, that are carried on the data bus occupying time slots 1 through 15 and 17 through 31. the first time slot (time slot 0) in the signaling highway is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the positions of the time slot 0 bits in this frame are the same as found in time slot 0 of the e1 frame format. it is not required that the time slot 0 bits from the signaling highway carry the frame alignment pattern in fas frames or have bit 2 in nfas frames set to a 1. the e1fx8 generates a new time slot 0 and does not use any of the information from ttsign. the sync pulse (ttfrmn) determines the start of each frame. in figure 44 below the abcd signaling states associated with each of the time slots are carried in the last four bits of each signaling bus time slot. thus, signaling is available for all telephone channels every frame. the first four bits in each signaling bus time slot may be set to zero. the e1fx8 inserts the signaling bits from the signal- ing highway into the corresponding time slot 16 positions for transmission on the e1 line if enabled by control bits tse1 through tse30 in registers x+ech, x+edh, x+eeh and x+efh. figure 44 shows the operation of the gapped clock or marker output ttauxn as well as the auxiliary input ttaixn. ttauxn is shown with a marker output for time slot 0. the 32 control bit pairs tc1cc/tc0cc in reg- isters x+112h through x+118h determine the source of each transmitted time slot (c = 0 - 31); it can come from the ttdatn, ttaixn, the idle code insertion register (x+119h) or a digital milliwatt generator. control bit tchmk (bits 7) in register x+110h controls the ttauxn signal. tchmk set to 1 selects a channel marker (ttauxn high for 8 clock periods of selected time slot). control bit ulaw (bit 2) in register x+06h selects the coding law used to generate the digital milliwatt. the table below shows the options described (where x=don?t care). - 94 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 44. transmit highway - data mode tc1cc tc0cc tchmk ulaw action for the selected time slot 0 0 x x normal operation. the time slot (c= 1 - 31) is transmitted intact from the data highway, ttdatn. the ttaixn lead is disabled. 0 1 0 x fractional e1 service. 64 kbit/s gapped clock provided on the ttauxn lead, and data from ttaixn lead is multiplexed into transmit bit stream. 0 1 1 x fractional e1 service. channel marker provided on the ttauxn lead, and data from ttaixn lead is multiplexed into transmit bit stream. 1 0 x x insert microprocessor-written idle code value from register x+119h. no gapped clock or channel marker generation on the ttauxn lead. the ttaixn lead is disabled. 1 1 x 0 a-law digital milliwatt generated for the time slot selected. no gapped clock or marker channel generation on ttauxn lead. the ttaixn lead is disabled. 1 1 x 1 mu-law digital milliwatt generated for the time slot selected. no gapped clock or marker channel generation on ttauxn lead. the ttaixn lead is disabled. ttclkn time slot 0 time slot 1 time slot 2 time slot 31 ttdatn 8 bits per channel ----abcd ----abcd ---aabcd ----abcd ttsign 125 s (frame) abcd bits for ts#1 data bits for ts #1 data bits for ts#2 abcd bits for ts#2 abcd bits for ts#30 data bits for ts#30 note: sync offset = 00 hex ttfrmn fas/nfas ttaixn ttauxn marker shown for time slot 0 pulse width = 488 ns - 95 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive highway with fractional e1 support in the data mode, the receive highway for each framer carries information from the e1fx8 to the system. like the transmit path, the receive highway is also subdivided into two time division multiplexed buses, one for data (rtdatn), and one for signaling (rtsign), where n represents one of the eight framers. the two buses are synchronous with the highway clock (rtclkn), which has a clock rate of 2048 khz. the clock (rtclkn) is either an output to the system or an input from the system. the system clock (rtclkn) or the line clock (rclkn) may be the input clock source for the slip buffer when it is enabled. usually the system clock (rtclkn) is used. the e1fx8 must be set to source the clock (rtclkn) as an output when the slip buffer is bypassed. the receive slip buffer for a framer is disabled when a 0 is written to the rxsbe bit (bit 5) in the reg- ister x+11bh. the clock source selection is determined by the rxcke bit (bit 7) in register x+11bh. a 0 writ- ten into this bit position selects the system clock (rtclkn) as the source clock. in addition to controlling the source of the clock, control bit rxcke also controls the source of the synchronization pulse. the data highway is a single bit-serial bus organized into 256-bit groups called frames, with the bits in each group numbered 1 through 256. each frame consists of 32 time slots numbered from 0 to 31, as shown in fig- ure 45. time slot 0 carries the frame synchronization pattern, multiframe pattern for the crc-4 multiframe option which uses the international bits, rai bits and sa4 through sa8 national bits. time slot 0 is output on rtdatn as it is received from the e1 line. also note that the beginning of each frame is identified by an active high synchronization pulse (rtfrmn), one (rtclkn) clock cycle wide, which occurs every 125 s, normally at the beginning of each frame. the position of the rtfrmn pulse is programmable to any bit position within the data bus frame using control bits rfrm7-rfrm0 in register 02eh. the synchronization pulse is aligned to bit 1 in time slot 0 in every frame when a value of 00h is written into this register. data to the data highway may be enabled on a per time slot basis from the e1 line. control bits rde1 through rde31 in control registers x+3ch, x+3dh, x+3eh and x+3fh when set to a 1 enable the time slot data from the line for the selected time slots. the signaling bus (rtsign) is also divided into 256-bit frames. each signaling frame consists of 120-bits of signaling information for the 30 telephone channels, numbered from 1 to 30, that are carried on the data bus occupying time slots 1 through 15 and 17 through 31. the first time slot (time slot 0) in the signaling highway is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the content of the time slot 0 bits in each frame are the same as found in time slot 0 of the received e1 frame. the sync pulse (rtfrmn) determines the start of each frame. in figure 45 below the abcd signaling states associated with each of the data time slots are carried in the last four bits of a signaling bus time slot. the first four bits in each signaling bus time slot are set to zero. the e1fx8 inserts the signaling bits from the line onto the signaling highway if enabled by control bits rse1 through rse30 in registers x+e8h, x+e9h, x+eah and x+ebh (after debouncing the signal, if debouncing is selected) every frame. figure 45 shows the operation of the gapped clock or marker output rtauxn. rtauxn is shown with a marker output for time slot 0. the 32 control bits rfchc in registers x+1bh through x+1eh determine the signal on rtauxn. control bit rchmk (bits 7) in register x+1ah controls the selected rtauxn signal. rchmk set to 1 selects a channel marker (rtauxn high for 8 clock periods of selected time slot). the table below shows the options described (where x=don?t care). rfchc rchmk action for the selected time slot 0 x normal operation. channel not selected for fractional e1 service. rtauxn lead low. 1 0 fractional e1 service. 64 kbit/s gapped clock provided on the rtauxn lead. 1 1 fractional e1 service. 64 kbit/s channel marker provided on the rtauxn lead. - 96 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 45. receive highway - data mode data and signaling inversion to accommodate different system applications either the data (time slots) or the signaling (abcd) may be inverted to or from the system interface. alternate digit inversion (either odd or even bits) is also provided. this feature is available per e1. time slot 0 is not inverted or altered by these control bits. control bits rdinv and rsinv (bits 7 and 6) in register x+04h, when set to 1, invert the time slot data to output lead rtdatn and the signaling bits to output lead rtsign, respectively. control bits tdinv and tsinv (bits 5 and 4) in register x+04h, when set to 1, invert the time slot data input from leads ttdatn and ttaixn and the signaling bits input from lead ttsign, respectively. control bit rdadi and tdadi (bits 3 and 2) in register x+04h invert the even bits of rtdatn and ttdatn respectively if set to 1 after inversion if any by rdinv or tdinv. the table below indicates the options (where x=don?t care). rdinv rdadi rsinv tdinv tdadi tsinv action taken on highways 0 0 0 x x x received data, and signaling not inverted from line to rtdatn/rtsign. 0 0 1 x x x signaling bits only on rtsign inverted (time slots 1 through 31). 1 0 0 x x x rtdatn inverted (time slots 1 through 31). 0 1 0 x x x even bits on rtdatn time slots 1 through 31 inverted. 1 1 0 x x x odd bits on rtdatn time slots 1 through 31 inverted. 1 0 1 x x x even bits on rtdatn time slots 1 through 31 inverted. signaling bits only on rtsign inverted (time slots 1 through 31). 1 1 1 x x x odd bits on rtdatn time slots 1 through 31 inverted; signaling bits only on rtsign inverted (time slots 1 through 31). x x x 0 0 0 data to be transmitted as received on ttdatn/ttsign. rtclkn time slot 0 time slot 1 time slot 2 time slot 31 rtdatn 8 bits per channel ----abcd ----abcd ---aabcd ----abcd rtsign 125 s (frame) abcd bits for ts#1 data bits for ts #1 data bits for ts#2 abcd bits for ts#2 abcd bits for ts#30 data bits for ts#30 note: sync offset = 00 hex rtfrmn fas/nfas rtauxn marker shown for time slot 0 pulse width = 488 ns - 97 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers mvip mode the mvip mode is enabled when a high is placed on the conf0 lead and a low is placed on the conf1 lead. transmit highway in the mvip mode, the transmit highway for each framer in the e1fx8 carries input information from the sys- tem. the highway for framer n is subdivided into two time division multiplexed buses, one for data (ttdatn), and one for signaling (ttsign). the two buses are synchronous with the highway clock (ttclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two time slots corresponding to the time slots on a framed e1 line. the frame start is identified by an active low synchronization pulse (ttfrmn), which is one (ttclkn) clock cycle wide and occurs every 125 microseconds. the position of the ttfrmn pulse is programmable to any bit position within the frame using control bits tfrm7 - tfrm0 in register 02fh. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the signaling bus (ttsign) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 30 time slots carry the abcd signaling bits associated with the 30 telephone channels. time slots 0 and 16 do not carry signaling information. the first time slot (time slot 0) in the signaling highway is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the positions of the time slot 0 bits in this frame are the same as found in time slot 0 of the e1 frame format. it is not required that the time slot 0 bits from the signaling highway carry the frame alignment pattern in fas frames or have bit 2 in nfas frames set to a 1. the e1fx8 generates a new time slot 0 and does not use any of the information from ttsign. the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the sig- naling buffer is updated every other frame. the line signaling states are updated once every sixteen frames per the time slot 16 signaling positions. in figure 46 below the abcd signaling states associated with each of the telephone channels is carried in the last four bits of a signaling bus time slot. the first four bits in each signaling bus time slot may be set to zero. the e1fx8 inserts the signaling bits from the signaling highway into time slot 16 positions if enabled by control bits tse1 through tse30 in registers x+ech, x+edh, x+eeh and x+efh. figure 46 shows the basic operation in mvip mode. the transmit slip buffer must always be enabled by control bit txsbe (bit 5) in register x+11ch being set to a 1 to provide clock rate adjustment between the 2.048 mhz backplane and the 2.048 mhz line. x x x 0 0 1 signaling bits only from ttsign inverted (time slots 1 through 31) x x x 1 0 0 ttdatn inverted (time slots 1 through 31). x x x 0 1 0 even bits from ttdatn time slots 1 through 31 inverted. x x x 1 1 0 odd bits from ttdatn time slots 1 through 31 inverted. x x x 1 0 1 even bits from ttdatn time slots 1 through 31 inverted; signaling bits only from ttsign inverted (time slots 1 through 31). x x x 1 1 1 odd bits from ttdatn time slots 1 through 31 inverted. signaling bits only from ttsign inverted (time slots 1 through 31). rdinv rdadi rsinv tdinv tdadi tsinv action taken on highways - 98 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 46. transmit highway - mvip mode receive highway in the mvip mode, the receive highway for each framer carries output information from the e1fx8 to the sys- tem. the highway for framer n is subdivided into two time division multiplexed buses, one for data (rtdatn), and one for signaling (rtsign). the two buses are synchronous with the highway clock (rtclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two time slots corresponding to the time slots from the framed e1 line. the frame start is identified by an active low synchronization pulse (rtfrmn), which is one (rtclkn) clock cycle wide and occurs every 125 microseconds. the position of the rtfrmn pulse is programmable by setting the values of the control bits rfrm7 - rfrm0 in register 02eh. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the signaling bus (rtsign) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 30 time slots carry the abcd signaling bits associated with the 30 telephone channels. time slots 0 and 16 do not carry signaling information. time slot 0 carries the received time slot 0 from the e1 line and time slot 16 carries the signals from time slot 16 frame 1 (0000 x0,y,x1,x2). the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the first four bits in each time slot are 0000. in figure 47 below, the abcd signaling states associated with each of the telephone channels are carried in the last four bits of a signaling bus time slot. the e1fx8 inserts the signaling bits from the signaling buffer into the signaling highway bit positions; if enabled by control bits rse1 through rse30 in registers x+e8h, x+e9h, x+eah and x+ebh, the signaling bits from the time slot 16 positions from the line side are inserted into the signaling buffer. the signaling highway is updated from the signaling buffer every frame. the signaling buffer is updated by the line every sixteen frames. 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 fas/nfas - - - -abcd- - - -abcd- - - -abcd- - - -abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #30 abcd bits for ch #2 abcd bits for ttfrmn ttclkn ttdatn ttsign si 1 r sa4 sa5 sa6 sa7 sa8 sixxxxxxx abcd bits for ch #1 frame f+1 frame f 18 18 18 18 18 ch #30 notes: si = international bits r = remote alarm indication (rai) bit, known as ts0 a-bit. san = national bits (n = 4-8) abcd = signaling bits for channel c (1-30). time slot 16 in the ttsign signals has the same format as frame 0 of the cas multiframe. - 99 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 47. receive highway - mvip mode data and signaling inversion to accommodate different system applications either the data (time slots) or the signaling (abcd) may be inverted to or from the system interface. alternate digit inversion (either odd or even bits) is also provided. this feature is available per e1. time slot 0 is not inverted or altered by these control bits. control bits rdinv and rsinv (bits 7 and 6) in register x+04h, when set to 1, invert the time slot data to output lead rtdatn and the signaling bits to output lead rtsign, respectively. control bits tdinv and tsinv (bits 5 and 4) in register x+04h, when set to 1, invert the time slot data input from leads ttdatn and ttaixn and the signaling bits input from lead ttsign, respectively. control bit rdadi and tdadi (bits 3 and 2) in register x+04h invert the even bits of rtdatn and ttdatn respectively if set to 1 after inversion if any by rdinv or tdinv. the table below indicates the options (where x=don?t care). rdinv rdadi rsinv tdinv tdadi tsinv action taken on highways 0 0 0 x x x received data, and signaling not inverted from line to rtdatn/rtsign. 0 0 1 x x x signaling bits only on rtsign inverted (time slots 1 through 31). 1 0 0 x x x rtdatn inverted (time slots 1 through 31). 0 1 0 x x x even bits on rtdatn time slots 1 through 31 inverted. 1 1 0 x x x odd bits on rtdatn time slots 1 through 31 inverted. 1 0 1 x x x even bits on rtdatn time slots 1 through 31 inverted; signaling bits only on rtsign inverted (time slots 1 through 31). 1 1 1 x x x odd bits on rtdatn time slots 1 through 31 inverted; signaling bits only on rtsign inverted (time slots 1 through 31). x x x 0 0 0 data to be transmitted as received on ttdatn/ttsign. 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 fas/nfas 0 0 0 0abcd0 0 0 0abcd- 0 0 0abcd0 0 0 0abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #30 abcd bits for ch #2 abcd bits for rtfrmn rtclkn rtdatn rtsign si 1 r sa4 sa5 sa6 sa7 sa8 si0011011 abcd bits for ch #1 frame f+1 frame f 18 18 18 18 18 ch #30 notes: si = international bits r = remote alarm indication (rai) bit, known as ts0 a-bit. san = national bits (n = 4-8) abcd = signaling bits for channel c (1-30). time slot 16 in the rtsign signals has the same format as frame 0 of the cas multiframe. - 100 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers h-mvip/h.100 mode the h-mvip mode is enabled when a low is placed on the conf0 lead and a high is placed on the conf1 lead with control bit dintf (bit 1) in register 00bh set to a 0. h.100 mode is enabled when a low is placed on the conf0 lead and a high is placed on the conf1 lead with control bit dintf (bit 1) in register 00bh set to a 1. operationally, the two modes are the same except the width of ttrfm1,5 and rtfrm1,5 is two clock cycles wide in h.100 mode and four clock cycles wide in h-mvip mode. h.100 pci level drivers and receivers are not supplied in the h.100 mode. transmit highway the 8 mbit/s h-mvip/h.100 mode provides dual transmit highways, each of which is shared by a group of four framers (1-4 and 5-8). each transmit highway consists of a data bus (ttdat1, 5), a signaling bus (ttsig1, 5), a clock (ttclk1, 5), and a synchronization signal (ttfrm1, 5), with an h.100 option for pulse width. the data and signaling time slots for each of the four framers are byte-interleaved on the data and signaling highways, starting with framer 1 (or 5) bit 1 of time slot 0, followed by framer 1 (or 5) bits 2 through 8 of time slot 0, then framer 2 (or 6) bits 1 through 8 of time slot 0, and so on, ending with framer 4 (or 8) bits 1 through 8 of time slot 31. in this mode, the separate data and signaling highways operate at 8.192 mbit/s. however, the clock rate is 16.384 mhz. the transmit system interface is synchronized by pulses that occur at 125-microsecond intervals. the transmit slip buffer must be enabled in each of the framers. auxiliary inputs and gapped clocks are not provided in this mode. figure 48 below shows the general structure for the framer group n=1-4. figure 48. transmit data and signaling highways - 8 mbit/s h-mvip/h.100 modes x x x 0 0 1 signaling bits only from ttsign inverted (time slots 1 through 31) x x x 1 0 0 ttdatn inverted (time slots 1 through 31). x x x 0 1 0 even bits from ttdatn time slots 1 through 31 inverted. x x x 1 1 0 odd bits from ttdatn time slots 1 through 31 inverted. x x x 1 0 1 even bits from ttdatn time slots 1 through 31 inverted; signaling bits only from ttsign inverted (time slots 1 through 31). x x x 1 1 1 odd bits from ttdatn time slots 1 through 31 inverted; signaling bits only from ttsign inverted (time slots 1 through 31). rdinv rdadi rsinv tdinv tdadi tsinv action taken on highways ttfrm1,5 ttdat1,5 ttsig1,5 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 dts0 dts31 dts31 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 sts0 sts31 sts31 sts0 sts0 sts0 16 clock cycles (8 bits) wide note: the data and signaling frame formats for each framer are the same as found in the 2 mbit/s mvip mode. framer number n signaling time slot number t framer number n data time slot number t 125 s 4 clock cycles (2 bits) wide hmvip 2 clock cycles (1 bit) wide h.100 - 101 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the frame start is identified by an active low synchronization pulse (ttfrm1,5), which is either two (h.100) or four (h-mvip) ttclk1,5 clock cycles wide and occurs every 125 microseconds. the position of the ttfrm1,5 pulse is programmable to any of 256 positions within the frame using control bits tfrm7 - tfrm0 in register 02fh. the synchronization pulse is aligned to straddle bit 8 of time slot 31 of framer no. 4 (or 8) and bit 1 in time slot 0 of framer no. 1 (or 5) when a value of 00h is written into this register. each value of 01h added to this register shifts the synchronization pulse 8 ttclk1,5 clock cycles earlier. receive highway the 8 mbit/s h-mvip/h.100 mode provides dual receive highways, each of which is shared by a group of four framers (1-4 and 5-8). each receive highway consists of a data bus (rtdat1, 5), a signaling bus (rtsig1, 5), a clock (rtclk1, 5), and a synchronization signal (rtfrm1, 5), with an h.100 option for pulse width. the data and signaling time slots for each of the four framers are byte-interleaved on the data and signaling high- ways, starting with framer 1 (or 5) bit 1 of time slot 0, followed by framer 1 (or 5) bits 2 through 8 of time slot 0, then framer 2 (or 6) bits 1 through 8 of time slot 0, and so on, ending with framer 4 (or 8) bits 1 through 8 of time slot 31. in this mode, the separate data and signaling highways operate at 8.192 mbit/s. however, the clock rate is 16.384 mhz. the receive system interface is synchronized by pulses that occur at 125-microsec- ond intervals. the receive slip buffer must be enabled in each of the framers. auxiliary inputs and gapped clocks are not provided in this mode. figure 49 below shows the general structure for the framer group n=1-4. the frame start is identified by an active low synchronization pulse (rtfrm1,5), which is either two (h.100) or four (h-mvip) rtclk1,5 clock cycles wide and occurs every 125 microseconds. the position of the rtfrm1,5 pulse is programmable to any of 256 positions within the frame using control bits rfrm7-rfrm0 in register 02eh. the synchronization pulse is aligned to straddle bit 8 of time slot 31 of framer no. 4 (or 8) and bit 1 in time slot 0 of framer no. 1 (or 5) when a value of 00h is written into this register. each value of 01h added to this register shifts the synchronization pulse 8 rtclk1,5 clock cycles earlier. figure 49. receive data and signaling highways - 8 mbit/s h-mvip/h.100 modes data and signaling inversion to accommodate different system applications either the data (time slots) or the signaling (abcd) may be inverted to or from the system interface. alternate digit inversion (either odd or even bits) is also provided. this feature is available per e1. time slot 0 is not inverted or altered by these control bits. control bits rdinv and rsinv (bits 7 and 6) in register x+04h, when set to 1, invert the time slot data to output lead rtdatn and the signaling bits to output lead rtsign, respectively. control bits tdinv and tsinv (bits 5 and 4) in register x+04h, when set to 1, invert the time slot data input from leads ttdatn and ttaixn and the signaling bits rtfrm1,5 rtdat1,5 rtsig1,5 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 dts0 dts31 dts31 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 sts0 sts31 sts31 sts0 sts0 sts0 16 clock cycles (8 bits) wide note: the data and signaling frame formats for each framer are the same as found in the 2 mbit/s mvip mode. framer number n signaling time slot number t framer number n data time slot number t 125 s 4 clock cycles (2 bits) wide hmvip 2 clock cycles (1 bit) wide h.100 - 102 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers input from lead ttsign, respectively. control bit rdadi and tdadi (bits 3 and 2) in register x+04h invert the even bits of rtdatn and ttdatn respectively if set to 1 after inversion if any by rdinv or tdinv. the table below indicates the options (where x=don?t care). since rdinv, rdadi, rsinv, tdinv, tdadi and tsinv are controls per e1, the actions taken are per framer, not on the entire highway. framing frame structure the basic frame structure of the 2048 kbit/s e1 signal consists of thirty-two 8-bit time slots, or 256 bits, and has a duration of 125 microseconds (8,000 frames per second). each time slot provides a 64 kbit/s channel. the thirty-two time slots are numbered 0 to 31, and the time slot bits are numbered 1 to 8. the first bit in a time slot to be received and transmitted is bit 1. framing information is carried in time slot 0, and signaling information, if it is assigned for channel associated signaling (cas), is carried in time slot 16. framing information for aligning the e1 frame is carried in time slot 0, using a two-frame sequence that alter- nates for consecutive frames. time slot 0 in the first frame carries the frame alignment pattern of x0011011. the second frame carries the pattern of x1xxxxxx, so that bit 2 identifies the first and second frames. the other bits in time slot 0, which are designated as x and are not used for frame alignment, are assigned for national, alarm and international use. the following table illustrates the framing pattern and bit assignment for time slot 0 when assigned to carry the basic framing format. where: si is reserved for international use. rai is defined as a remote alarm indication a-bit (true state is equal to 1) sa4-sa8 bits are reserved for national use. rdinv rdadi rsinv tdinv tdadi tsinv action taken per framer 0 0 0 x x x received data and signaling not inverted from line to system 0 0 1 x x x signaling bits on rtsig1,5 selected time slots inverted. 1 0 0 x x x rtdat1,5 selected time slots inverted. 0 1 0 x x x even bits on rtdat1,5 selected time slots inverted. 1 1 0 x x x odd bits on rtdat1,5 selected time slots inverted. 1 0 1 x x x even bits on rtdat1,5 selected time slots inverted. signaling bits on rtsign selected time slots inverted. 1 1 1 x x x odd bits on rtdat1,5 selected time slots inverted. signaling bits on rtsign selected time slots inverted. x x x 0 0 0 data to be transmitted as received on ttdat1,5/ttsig1,5. x x x 0 0 1 signaling bits on ttsig1,5 selected time slots inverted. x x x 1 0 0 ttdat1,5 selected time slots inverted. x x x 0 1 0 even bits from ttdat1,5 selected time slots inverted. x x x 1 1 0 odd bits from ttdat1,5 selected time slots inverted. x x x 1 0 1 even bits on ttdat1,5 selected time slots inverted. signaling bits on ttsign selected time slots inverted. x x x 1 1 1 odd bits on ttdat1,5 selected time slots inverted. signaling bits on ttsign selected time slots inverted. frametypebit 12345678 1fassi (#1)0011011 2 nfas si (#2) 1 rai sa4 sa5 sa6 sa7 sa8 - 103 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers to provide end to end performance monitoring and additional framing protection against the emulation of a frame alignment pattern in the data stream, time slot 0 can be assigned to carry a 16-frame multiframe. the 16-frame multiframe carries a 001011 multiframe alignment pattern, crc-4 check, and two e-bits in the bit 1 position of two sub-multiframes designated as sf i and sf ii, as shown below: where: c1-c4 are the crc-4 bits. rai is defined as a remote alarm indication a-bit (true state is equal to 1) sa4-sa8 are reserved for national use. e-bits are used for a crc-4 error indication to or from far end (far end block error) fas is the frame alignment signal nfas is the non frame alignment signal frame alignment the e1fx8 supports two frame alignment operating modes in each framer: basic frame alignment detection, and frame alignment detection with a crc-4 validation. the receive framer circuit also employs an offline framing algorithm, where the payload is sent to the terminal side output even during loss of frame (together with rtfrmn and rtclkn, if these are framer outputs). this is advantageous, since re-framing usually occurs at the same frame position. frame alignment and framing pattern generation may be optionally applied to the receive path or the transmit path of the e1fx8 as shown in the table below. sub-fframetypebit 12345678 sf i 0fasc10011011 1 nfas 0 1 rai sa4 sa5 sa6 sa7 sa8 2fasc20011011 3 nfas 0 1 rai sa4 sa5 sa6 sa7 sa8 4fasc30011011 5 nfas 1 1 rai sa4 sa5 sa6 sa7 sa8 6fasc40011011 7 nfas 0 1 rai sa4 sa5 sa6 sa7 sa8 sf ii 8fasc10011011 9 nfas 1 1 rai sa4 sa5 sa6 sa7 sa8 10fasc20011011 11 nfas 1 1 rai sa4 sa5 sa6 sa7 sa8 12fasc30011011 13 nfas e 1 rai sa4 sa5 sa6 sa7 sa8 14fasc40011011 15 nfas e 1 rai sa4 sa5 sa6 sa7 sa8 rtfm x+01h:7 ttfm x+01h:6 framing actions taken by e1fx8 0 0 the receive path is set to detect frame alignment and the transmit path generates time slot 0 as determined by control bits crcmd1,0, bfaa, crca, aags and aiw. - 104 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers basic frame alignment detection has two algorithms: standard and frame hold-off. the selection is deter- mined by control bit bfaa (bit 5) in the framer configuration register x+01h for each framer. when control bit bfaa is written with a 0, the standard algorithm is selected. when written with a 1, the frame hold-off algo- rithm is selected. the standard framing algorithm operates continuously according to the following steps: 1- a valid frame alignment signal x0011011 is detected in time slot 0 of frame f (fas frame). 2- the absence of a frame alignment signal is verified by checking that bit 2 is a 1 in time slot 0 of frame f+1 (nfas frame). 3- a valid frame alignment signal x0011011 is detected in time slot 0 of frame f+2 (fas frame). if these criteria are met by three consecutive frames, then the framer is declared to be aligned. if step 2 fails, a new search for frame alignment is started in the next bit position of the current frame. the frame hold-off algorithm uses the same steps as found in the standard frame alignment search, except that the new search is initiated in the next bit position in the next frame. when the e1fx8 is out of frame alignment, status bit oof (bit 5) in register x+10h is set to a 1. an associated mask bit moof a latched event bit loof, a performance value poof and a fault value foof are all bit 5 of registers x+14h, x+11h, x+12h and x+13h respectively. if control bit autrai (bit 0) in register x+08h is set to a 1, rai (bit 3 or ?a? bit) in nfas frames will also be set to a 1. the e1fx8 also supports frame alignment detection by validating a crc-4 multiframe check sequence in addi- tion to either of the basic frame alignment detection sequences. each framer in the e1fx8 can be configured for two types of crc-4 multiframe check: manual or an automatic mode. the manual mode is selected by writ- ing a 0 to control bit crca (bit 3) in register x+01h. in the manual mode, after frame alignment has been achieved (see above), multiframe alignment occurs if two valid crc multiframe signals are detected within 8 milliseconds. after crc multiframe is established the e1fx8 begins checking the crc bits. if multiframe can- not be achieved within the 8 millisecond period, a new search for frame alignment is initiated in parallel as well as a new search for multiframe alignment, and an out of crc-4 multiframe status indication oofm (bit 2) in register x+10h continues. an associated mask bit moofm, a latched event bit loofm, a performance value poofm and a fault value foofm are all bit 2 of registers x+14h, x+11h, x+12h and x+13h respectively. when con- trol bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0, an indication of crc-4 multi- frame alignment loss is sent to the distant end by setting the two e-bits in time slot 0 (bit 1 in frames 13 and 15) to zero. 0 1 the receive path is set to detect frame alignment as determined by control bits crcmd1,0, bfaa, crca, aags and aiw. the transmit path is transparent; data is passed through from ttdatn directly or via the transmit slip buffer unaltered; ttfrmn has no influence. slip buffer slips affect a group of 256 bits uniformly (skipped or repeated). 1 0 the transmit path generates time slot 0 as determined by control bits crcmd1,0, bfaa, crca, aags and aiw. the receive path is transparent. every 256 line bits are passed through to rtdatn directly or via the receive slip buffer unaltered; rtfrmn has no relation- ship to time slot 0. slip buffer slips affect a group of 256 bits uniformly (skipped or repeated). 1 1 the receive and transmit paths are transparent. every 256 line bits are passed through to rtdatn directly or via the receive slip buffer unaltered; rtfrmn has no relationship to time slot 0. data is passed through from ttdatn directly or via the transmit slip buffer unaltered; ttfrmn has no influence. slip buffer slips affect a group of 256 bits uniformly (skipped or repeated). rtfm x+01h:7 ttfm x+01h:6 framing actions taken by e1fx8 - 105 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the automatic mode is selected by writing a 1 to control bit crca (bit 3) in register x+01h. within the auto- matic mode several options exist for searching for multiframe alignment; itu-t g.706, ets 300 011 and tbr 04 with itaab note 75 support. the table below describes the various options and how they affect the local and transmitted alarms. alarm transmission assumes that control autrai (bit 0) in register x+08h is set to a 1. for itu-t g.706 control bits crcmd0, bfaa, crca, aags and aiw = 0x100. initially oof and oofm sta- tus is active, rai is set to a 1 and the e-bits are set to 0; the first basic frame alignment declaration clears rai to 0 and oof status where they remain until basic frame alignment is lost. when multiframe alignment is found, oofm status is cleared, the e-bits are set to 1 and are only set to 0 when a sub-multiframe is found to have bad crc-4; each sub-multiframe with bad crc-4 is counted in a 10 bit error counter crc0 - crc9 with overflow bit crco in registers x+f2h and x+f3h with one-second shadow counter lcrc0 - lcrc9 and lcrco in registers x+f0h and x+f1h. if multiframe is not found by the process described above within a 400 millisecond search period, the framer assumes that the distant end is not configured for crc multiframe pat- tern, and sets a status bit, ncrc4 (bit 7) in register x+18h to a 1. once the 400 millisecond timer times out, the e1fx8 then inhibits further crc-4 processing. when control bits crcmd1 and crcmd0 (bits 2 and 1) in register x+07h are set to x0, an indication of crc-4 multiframe alignment loss is sent to the distant end by keeping the two e-bits in time slot 0 to zero. for isdn applications (itu-t i.431 or ets 300 011; non interworking) control bits crcmd0, bfaa, crca, aags and aiw = 00110. initially oof and oofm status is active, rai is set to a 1 and the e-bits are set to 1; the first basic frame alignment declaration (using the standard algorithm) clears rai to 0 and oof status. when multiframe alignment is found, oofm status is cleared, the e-bits remain set to 1 and are only set to 0 when a sub-multiframe is found to have bad crc-4; each sub-multiframe with bad crc-4 is counted in a 10 bit error counter crc0 - crc9 with overflow bit crco with one-second shadow counter lcrc0 - lcrc9 and lcrco. if multiframe cannot be achieved within the 8 millisecond period, a new search for frame alignment is initiated in parallel as well as a new search for multiframe alignment, and an out of crc-4 multiframe status indication oofm (bit 2) in register x+10h remains. in addition the rai indication is sent until the parallel basic frame alignment is declared which clears rai to 0. if multiframe is not found within a 400 millisecond search period, the framer assumes that the distant end is not configured for crc multiframe pattern, and sets rai continuously to a 1 even with basic frame alignment found with status remaining in oofm. however, search- ing for multiframe alignment never ceases. for etsi isdn interworking applications (tbr 04 with itaab note 75) control bits crcmd0, bfaa, crca, aags and aiw = 00101. initially oof and oofm status is active, rai is set to a 1 and the e-bits are set to 0; the first basic frame alignment declaration (using the standard algorithm) clears rai to 0 and oof status where they remain until basic frame alignment is lost. when multiframe alignment is found, oofm status is cleared, the e-bits are set to 1 and are only set to 0 when a sub-multiframe is found to have bad crc-4; each sub-multiframe with bad crc-4 is counted in a 10 bit error counter crc0 - crc9 with overflow bit crco with one-second shadow counter lcrc0 - lcrc9 and lcrco. if multiframe cannot be achieved within the 8 milli- second period, a new search for frame alignment is initiated in parallel as well as a new search for multiframe alignment, and an out of crc-4 multiframe status indication oofm (bit 2) continues. if multiframe is not found within a 400 millisecond search period, the framer assumes that the distant end is not configured for crc multiframe pattern, and sets a status bit, ncrc4 (bit 7) in register x+18h to a 1, but continues further crc-4 processing. for both manual and automatic multiframe alignment the crc-4 pattern is checked, and an excessive crc error indication ecrce (bit 6) in register x+164h is set to 1 when 915 or more of the last 1000 crcs were received in error. an associated mask bit mecrce, a latched event bit lecrce, a performance value pecrce and a fault value fecrce are all bit 6 of registers x+166h, x+165h, x+167h and x+168h respectively. e crce forces an out of frame and is cleared when basic frame alignment is regained. the following table summarizes the con- trol bits associated with selection of the frame alignment algorithm for one of the eight framers (where x=don?t care):. - 106 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers crcmd1 x+07h:3 crcmd0 x+07h:2 bfaa x+01h:5 crca x+01h:3 aags x+01h:0 aiw x+0ah:0 framing actions 0 1 0 x x x frame alignment detector is enabled using the stan- dard algorithm. the crc-4 multiframe detector and generator are disabled. 0 1 1 x x x frame alignment detector is enabled using the frame hold-off algorithm. the crc-4 multiframe detector and generator are disabled. x 0 0 0 0 x frame alignment detector is enabled using the stan- dard algorithm. the crc-4 multiframe detector and generator are enabled for manual operation. in addi- tion, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zeros when the crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled, to count e-bit errors. x 0 1 0 0 x frame alignment detector is enabled using the frame hold-off algorithm. the crc-4 multiframe detector and generator are enabled for manual oper- ation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zeros when the crc-4 multiframe is lost. the 10-bit e-bit perfor- mance counter is also enabled, to count e-bit errors. x 0 0 1 0 0 itu-t g.706 interworking: frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10-bit crc counter is enabled. transmit e-bits are sent as zero when crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled for counting e- bit errors. 400 ms time-out for search; no rai after basic frame alignment. x 0 1 1 0 0 itu-t g.706 interworking: frame alignment detector is enabled using the frame hold-off algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zero when crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled for counting e-bit errors. 400 ms time-out for search; no rai after basic frame alignment. x 0 0 1 1 0 etsi isdn non-interworking: frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as one when crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled for counting e-bit errors. 400 ms time-out for setting/clearing rai after basic frame alignment but no multiframe alignment. no time-out for search. - 107 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers received e-bits are counted once the e1fx8 is in crc-4 multiframe alignment. each occurrence of a zero e-bit is counted in a 10 bit counter ebe0 - ebe9 with overflow bit ebeo in registers x+100h and x+101h. one-second shadow registers lebe9 - lebe0 and lebeo are located at x+feh and x+ffh. out of frame alignment an out of frame (oof) alarm is declared when a selected number of consecutive incorrect frame alignment patterns in time slot 0 is detected, or when 915 or more out of 1000 crc-4 are received in error (ecrce, bit 6 in register x164h). the oof alarm is indicated at bit 5 in register x+10h. an associated mask bit moof, a latched event bit loof, a performance value poof and a fault value foof are all bit 6 of registers x+14h, x+11h, x+12h and x+13h respectively. an incorrect frame alignment pattern is defined as an incorrect bit in at least one of the seven framing bits in an fas time slot 0, or an error (i.e., a 0) in bit 2 in time slot 0 in the next (nfas) frame. the number of incorrect frame alignment patterns in error is programmable using the oof1 and oof0 x 0 0 1 0 1 etsi isdn interworking: frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zero when crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled for count- ing e-bit errors. no time-out for search; no rai after basic frame alignment. x 0 x 1 1 1 not recommended. 1 1 0 0 x x frame alignment detector is enabled using the stan- dard algorithm. the crc-4 multiframe detector and generator are enabled for manual operation. in addi- tion, the receive 10-bit crc counter is enabled. the e-bits are always transmitted as 1s, if aags = 1; oth- erwise e-bits = 0 under oof. 1 1 1 0 x x frame alignment detector is enabled using the frame hold-off algorithm. the crc-4 multiframe detector is enabled for manual operation. in addition, the receive 10-bit crc counter is enabled. the e-bits are always transmitted as 1s, if aags = 1; oth- erwise e-bits = 0 under oof. 1 1 0 1 0 0 frame alignment detector is enabled using the stan- dard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. the e-bits are always transmitted as 1s, if aags = 1; oth- erwise e-bits = 0 under oof. the crc-4 counter is enabled. 1 1 1 1 0 0 frame alignment detector is enabled using the frame hold-off algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. the e-bits are always transmitted as 1s, if aags = 1; otherwise e-bits = 0 under oof. the crc-4 counter is enabled. 1 1 x 1 1 x not recommended 1 1 x 1 x 1 not recommended crcmd1 x+07h:3 crcmd0 x+07h:2 bfaa x+01h:5 crca x+01h:3 aags x+01h:0 aiw x+0ah:0 framing actions - 108 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers control bits (bits 2 and 1) in register x+01h. the out of frame alignment condition starts the resynchroniza- tion process for basic frame alignment. in addition, the software can also initiate a resynchronization of the frame alignment detector by writing a one to control bit rsync (bit 6) in register x+0ah. the following table lists the selection options for declaring an out of frame (oof) alarm. frame word errors (an incorrect bit in at least one of the seven framing bits in an fas time slot 0, or an error (i.e., a 0) in bit 2 in time slot 0 in a nfas frame) are counted in an eight bit counter fbe0-fbe7 with overflow bit fbeo in registers x+fch and x+fdh. one-second shadow registers lfbe9-lfbe0 and lfbeo are located at x+fah and x+fbh. either a change of basic frame alignment or a change of multiframe alignment may cause a new value to be loaded into the frame synchronization circuit after basic frame alignment (crc-4 disabled) multiframe align- ment (crc-4 enabled) have been achieved. this condition is indicated in status bit cfa (bit 3) in register x+10h. an associated mask bit mcfa, a latched event bit lcfa, a performance value pcfa and a fault value fcfa are all bit 3 of registers x+14h, x+11h, x+12h and x+13h respectively. loss of crc-4 multiframe alignment when the crc-4 feature is enabled, a crc-4 loss of multiframe indication oofm (bit 2) in register x+10h is generated if control bit eoocrc (bit 2) in register x+03h is set to a 1 and when basic frame alignment is lost either by consecutive incorrect basic frame alignment patterns or by 915 or more out of 1000 crc-4 received in error, as indicated by the oof alarm, bit 5 in register x+10h. the oofm bit is cleared only when multiframe alignment is regained. an associated mask bit moofm, a latched event bit loofm, a performance value poofm and a fault value foofm are all bit 2 of registers x+14h, x+11h, x+12h and x+13h respectively. the oofm bit is also set if a loss of time slot 16 multiframe occurs with control bit eoo16m (bit 1) in register x+03h set to a 1 and control bit ts16eic (bit 0) in register x+00h is set to a 1. transmit framer each of the eight transmit framers performs the following functions, unless the framer is configured for the transparent (unframed) mode of operation using the 2 mbit/s transmission mode or data mode interfaces only: - generates the framing pattern (x0011011) in alternating (fas) frames for time slot 0. - sets bit 2 to 1 in time slot 0 in (nfas) frames not carrying the framing pattern. - inserts either the international bits for the basic format, or the crc-4/e-bits with multiframe pattern for the crc-4 multiframe format into time slot 0. - inserts the national bits, and remote alarm indication bit, into nfas time slot 0. - inserts time slots 1-15 and 17-31 into the transmitted frame. - inserts time slot 16 as either a clear channel, or channel associated signaling (cas) information from the transmit signaling buffers. - locks time slot 0 and time slot 16 cas multiframes together for transmission. oof1 x01h:2 oof0 x01h:1 action 0 0 three consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0. 01 four consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0. 1 0 three consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0, or three consecutive incorrect bit 2 values of 0 in a nfas time slot 0. this setting is recommended for etsi applications. 1 1 four consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0, or four consecutive incorrect bit 2 values of 0 in a nfas time slot 0. - 109 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot 0 the basic framed mode of operation is selected by writing control bits crcmd1 (bit 3) and crcmd0 (bit 2) in register x+07h to 01 and control bits rtfm and ttfm (bits 7 and 6) in register x+01h are set to 0 to enable framing for either the receive or the transmit path respectively. the mode selection is common to both the transmit and receive sides of a framer channel but transparency is individually selectable. the international bits from the transmit signaling highway (available in transmission mode only) are inserted into bit 1 of time slot 0, unless the crc-4 feature is selected. the microprocessor can disable this path by writing a 0 to control bit tsis (bit 7) in register x+e3h, which freezes the values of the two international bits, located at bit 7 in reg- isters x90h (associated with fas) and xb0h (associated with nfas), and allows them to be written by the microprocessor. the crc-4 framing mode is selected by writing control bits crcmd1 (bit 3) and crcmd0 (bit 2) in register x+07h to x0 or 11. the insertion of the international bits from the signaling highway is disabled, and the trans- mit framer inserts the multiframe alignment pattern, the calculated crc-4 value and the e-bits as shown in the chart in the frame structure section above. the e-bit generation is internal to the framer within the e1fx8, and is not directly accessible by the microprocessor in the transmit direction. however, the e-bit may be set to a 0 or 1 initially and, depending on the framing mode options selectable by control bits crcmd1, crcmd0, aags, crca and aiw and the received framing pattern as described in the frame alignment section above, the e-bits may be fixed at a 0 or 1 or they may go from 1 to 0 to indicate each bad crc-4 received. the crc multiframe alignment pattern is generated by the framer. the time slot 16 (ts16) multiframe align- ment pattern is generated only when cas signaling types are selected by control bits typ1, typ0 (bits 7 and 6) in register x+134h (=10 or 01). ts16 multiframe alignment is meaningless in ts16 clear channel mode (typ1, typ0 = 00). ts16 multiframe alignment is independent of the device framing mode but is locked to crc-4 multiframe alignment for transmission to the e1 line when crc-4 multiframe alignment mode is selected. the remote alarm indication (rai) a-bit is assigned to bit 3 in alternating frames in both the framed and crc-4 mode of operation. when control bit autrai (bit 1) in register x+08h is set to 1, a loss of frame alignment on the receive side sets the transmitted rai bit to 1 for the duration of the alarm. the microprocessor can also write the state of the rai bit, independent of automatic rai insertion. when the microprocessor writes a 1 to control bit txrai (bit 6) in register x+06h, the rai bit is transmitted as a 1. in addition, when control bit extrai (bit 4) in register x+06h is written with a 1, a 1 in bit ?r? (bit 3) in time slot 0 nfas frames (odd frames) from the signaling highway in the transmission mode only will also result in an rai alarm being transmitted. see above for rai set after 400 millisecond time out in etsi mode. the seven-bit framing pattern (x0011011) in alternating (fas) frames for time slot 0, and the 1 value for bit 2 in time slot 0 in (nfas) frames not carrying the framing pattern (x1xxxxxx), are generated by the framer. each framer also has the capability of generating framing pattern errors in fas frames, bit 2 errors in alternat- ing (nfas) frames, and crc-4 errors. when control bit frme (bit 6) in register x+106h is set to 1, the trans- mitter sends the frame alignment pattern and the international bit (used as crc in crc-4 multiframe mode) in error for one fas frame. all the bits in the frame alignment sequence are inverted (si0011011 becomes si 1100100). this bit must be written with a 0 and then a 1 to send another fas error. when control bit nfase (bit 4) in x+106h is set to 1, the transmit framer sends bit 2 in time slot 0 as a 0 for a single nfas frame. this bit must be written with a 0 and then a 1 to send another nfas error. when control bit crce (bit 7) in register x+106h is set to 1, the crc-4 bits in time slot 0 are transmitted in the inverted state once if control bits crcmd1,0 (bits 3 and 2) in register x=07h are set to x0. to send another crc-4 error, this bit must be first written with a 0, and then a 1. - 110 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers national bit support full national bit support is provided for isdn (etsi 300 233), itu-t g.704 synchronization status messages (ssm) and cept irsm signaling (?en? bits). received national bits are stored in byte wide registers aligned to the crc-4 multiframe and byte wide registers which are provided for transmitting the national bits. the national bits can be sourced from the signaling highway, ttsign, in transmission mode. the national bits may also be assigned to the hdlc controller. the transmitted path for the individual national bits (sa4 to sa8) in time slot 0 in either framing mode can be assigned from the hdlc link (all system interface modes) or from the signaling highway (transmission mode only). in the crc-4 multiframe mode, when control bits tsa4s through tsa8s (bits 4-0) in register x+e3h are set to a 0, control bit bnal (bit 5) in register x+122h is set to a 0 and control bits sa4 through sa8 (bits 4-0) in register x+0ch are set to 0, the national bits can be sourced from registers xsa4(7-0), xsa5(7-0), xsa6(7-0), xsa7(7-0) and xsa8(7-0) in locations x+169h through x+16dh with bit 7 of each register trans- mitted in frame 2 of the multiframe, bit 6 in frame 4, etc. in either framing mode national bits received are stored in the receive slip buffer at location x+60h, desig- nated rnfas, in bits 4-0 if control bits rsa4s through rsa8s (bits 4-0) in register x+3bh are set to 1. when in rsa4s through rsa8s are set to 0, rnfas bit(s) 4-0 are frozen and can be written by the microprocessor. in transmission mode, the national bits are always read from rnfas and placed on the receive signaling highway rtsign in bits 4 - 8 of time slot 0 in nfas (odd numbered) frames. in the crc-4 multiframe mode, if control bit enrxnbr (bit 3) in register x+03h is set to a 1, national bits received are placed in registers rsa4(7-0), rsa5(7-0), rsa6(7-0), rsa7(7-0) and rsa8(7-0) in locations x+16fh through x+173h with bit 7 of each register storing the value received in frame 2, bit 6 storing the value received in frame 4, etc. received sa6 is further processed for identifying specific codes and for counting specific codes if control bit enrxnbr is set to a 1. read to clear status bits s68, s6a, s6c, s6e and s6f (bits 0, 1, 2, 3 and 4) in register x+175h when set to a 1, indicates that either code 1000, 1010, 1100, 1110 or 1111 was received for three sub-multi- frames in a row. read to clear status bit s6x (bit 5) in register x+175h when set to a 1, indicates another code was received for three sub-multiframes in a row. each time code 00x1 is received in a sub-multiframe, 10 bit sa6 counter no. 1, sa61(9-0), with overflow indicator sa16o in locations x+179h and x+17ah is pegged; this code corresponds to a far end error from isdn terminal equipment. shadow register bits lsa61(9-0) and lsa61o are located at x+177h and x+178h providing a one-second latched view if control bit srgen (bit 3) in register 00bh is set to a 1. each time code 001x is received in a sub-multiframe, 10 bit sa6 counter no. 2, sa62(9-0), with overflow indicator sa26o in locations x+17dh and x+17eh is pegged; this code corresponds to a far end error from isdn t reference point. shadow register bits lsa62(9-0) and lsa62o are located at x+17bh and x+17ch providing a one-second latched view if control bit srgen (bit 3) in register 00bh is set to a 1. when control bit bnal is a 1, all the national bits are transmitted from the signaling highway via a buffer. the microprocessor enables transmission of the national bits from the code registers xsa47-xsa40 through xsa87-xsa80 (in registers x+169h through x+16dh) by setting bits tsa4s-tsa8s (bits 4-0 in register x+e3h) to 0. note that writing bits tsa4s-tsa8s with zeros does not freeze bits 4-0 in register x+b0h, which is the transmit slip buffer location for nfas, therefor microprocessor writes of the sa bits at register x+b0h are not possible, since these bits are continuously updated from the system side. this is the recommended method of fixing the sa bits to a specific value per itu-t g.704 when using the basic framed mode. when con- trol bit bnal is written with a 0, the transmitted path will be either via the data link or via the signaling highway through the buffer. the bandwidth of the hdlc channel is controlled by control bits sa4-sa8 (bits 4-0) in reg- ister x+0ch. a 1 written to one or more bits selects those bits as the hdlc channel. for example, if control bits sa4-sa7 are set with a 1, then bits sa4 to sa7 in time slot 0 will transmit the hdlc channel providing a 16 kbit/s data link. the sa8 bit time slot 0 path will be from the signaling highway via the buffer. when a 1 is written to control bits sa4-sa8 and control bit bnal is set to a 0, hdlc flag characters are continuously sent in the national bits selected regardless of the setting of control bit eht (bit 7) in register x+126h. the opera- tion of the hdlc controller is described in the hdlc channel section below. the table below summarizes the national bit options (where x=don?t care): - 111 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers crcmd1,0 x+07h:3,2 bnal x+122h:5 tsa4/8s x+e3h:4/0 rsa4/8s x+3bh:4/0 sa4/8 x+0ch:4/0 national bit actions 01 0 x 0 0 selected national bits to e1 line from tnfas (x+b0h) and received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 01 0 x 0 1 selected national bits to e1 line from hdlc con- troller and received national bits not written to rnfas (x+60h) but sent to hdlc controller. val- ues in rnfas sent to rtsign (transmission mode). 01 0 x 1 0 selected national bits to e1 line from tnfas (x+b0h) and received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). 01 0 x 1 1 selected national bits to e1 line from hdlc con- troller and received national bits written to rnfas (x+60h) and sent to hdlc controller. values from e1 line sent to rtsign (transmission mode). 01 1 0 0 0 selected national bits to e1 line from tnfas (x+b0h) and received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 01 1 0 0 1 selected national bits to e1 line from tnfas (x+b0h) and received national bits not written to rnfas (x+60h) but sent to the hdlc controller. values in rnfas sent to rtsign (transmission mode). 01 1 1 0 0 selected national bits to e1 line from ttsign (transmission mode) and received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 01 1 1 0 1 selected national bits to e1 line from ttsign (transmission mode) and received national bits not written to rnfas (x+60h) but sent to hdlc controller. values in rnfas sent to rtsign (transmission mode). 01 1 0 1 0 selected national bits to e1 line from code regis- ters xsa47-xsa40 through xsa87-xsa80 (in reg- isters x+169h through x+16dh) and received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). 01 1 0 1 1 selected national bits to e1 line from code regis- ters xsa47-xsa40 through xsa87-xsa80 (in reg- isters x+169h through x+16dh) and received national bits written to rnfas (x+60h) and hdlc controller. values from e1 line sent to rtsign (transmission mode). 01 1 1 1 0 selected national bits to e1 line from ttsign (transmission mode) and received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). - 112 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 01 1 1 1 1 selected national bits to e1 line from ttsign (transmission mode) and received national bits written to rnfas (x+60h) and to hdlc controller. values from e1 line sent to rtsign (transmission mode). 11 or x0 0 0 0 0 selected national bits to e1 line from xsa4 - xsa8. received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 11 or x0 0 0 0 1 selected national bits to e1 line from hdlc con- troller and received national bits not written to rnfas (x+60h) but sent to hdlc controller. val- ues in rnfas sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. 11 or x0 0 0 1 0 selected national bits to e1 line from xsa4 - xsa8. received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). 11 or x0 0 0 1 1 selected national bits to e1 line from hdlc con- troller and received national bits written to rnfas (x+60h) and sent to hdlc controller. values from e1 line sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. 11 or x0 0 1 0 0 selected national bits to e1 line from tnfas (x+b0h). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 11 or x0 0 1 0 1 selected national bits to e1 line from hdlc con- troller and received national bits not written to rnfas (x+60h) but sent to hdlc controller. val- ues in rnfas sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. 11 or x0 0 1 1 0 selected national bits to e1 line from tnfas (x+b0h). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). crcmd1,0 x+07h:3,2 bnal x+122h:5 tsa4/8s x+e3h:4/0 rsa4/8s x+3bh:4/0 sa4/8 x+0ch:4/0 national bit actions - 113 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 11 or x0 0 1 1 1 selected national bits to e1 line from hdlc con- troller and received national bits written to rnfas (x+60h) and sent to hdlc controller. values from e1 line sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. 11 or x0 1 0 0 0 selected national bits to e1 line from xsa4 - xsa8. received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 11 or x0 1 0 0 1 selected national bits to e1 line from code regis- ters xsa47-xsa40 through xsa87-xsa80 (in reg- isters x+169h through x+16dh). received national bits not written to rnfas (x+60h) but sent to hdlc controller. values in rnfas sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detec- tors and counters enabled if enrxnbr = 1. 11 or x0 1 0 1 0 selected national bits to e1 line from xsa4 - xsa8. received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). 11 or x0 1 0 1 1 selected national bits to e1 line from hdlc con- troller. received national bits written to rnfas (x+60h) and sent to hdlc controller. values from e1 line sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. 11 or x0 1 1 0 0 selected national bits to e1 line from tnfas (x+b0h). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits not written to rnfas (x+60h). values in rnfas sent to rtsign (transmission mode). 11 or x0 1 1 0 1 selected national bits to e1 line from tfnas (x+b0h). received national bits not written to rnfas (x+60h) but sent to hdlc controller. val- ues in rnfas sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. crcmd1,0 x+07h:3,2 bnal x+122h:5 tsa4/8s x+e3h:4/0 rsa4/8s x+3bh:4/0 sa4/8 x+0ch:4/0 national bit actions - 114 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers fast sync mode the e1fx8 provides a fast sync mode which may be used for testing purposes. the fast sync mode for the receiver side is selected when control bit rxfs (bit 1) in register x+1ffh is written with a 1 in the nrz mode and the rnegn/rscann is not being used for los input or counting code violations (see line interface selection above). a positive pulse on lead rscann that is one clock cycle wide in bit position 256 of the last frame in the crc-4 multiframe forces the framer into synchronization. it can occur repetitively at 2 ms inter- vals, or it can be pulsed once provided the received framing sequence is valid afterwards. the fast sync mode for the transmitter side is selected when control bit tdfme (bit 7) in register x+07h is writ- ten with a 1 in the nrz mode and tnegn/tdrvn is not being used as a drive bit (see line interface selection above). the tdrvn output in this mode is a one clock cycle wide pulse in bit position 256 of the last frame in the crc-4 multiframe that occurs every 2 ms if control bit tlmf (bit 5) in register x+07h is set to a 1; if tlmf is set to a 0, a pulse occurs in bit position 256 of every frame providing a 125 s signal. this allows an external device to be synchronized to the e1fx8. 11 or x0 1 1 1 0 selected national bits to e1 line from tnfas (x+b0h). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. received national bits written to rnfas (x+60h). values from e1 line sent to rtsign (transmission mode). 11 or x0 1 1 1 1 selected national bits to e1 line tfnas (x+b0h). received national bits written to rnfas (x+60h) and sent to hdlc controller. values from e1 line sent to rtsign (transmission mode). received national bits stored in rsa4 - rsa8 and sa6 code detectors and counters enabled if enrxnbr = 1. crcmd1,0 x+07h:3,2 bnal x+122h:5 tsa4/8s x+e3h:4/0 rsa4/8s x+3bh:4/0 sa4/8 x+0ch:4/0 national bit actions - 115 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers slip buffers the time slots 1-15 and 17-31 are inserted into the transmitted frame from the transmit slip buffer when it is enabled, or directly from the data highway, leads ttdatn and ttaixn when it is bypassed (2 mbit/s transmis- sion mode and data mode only). likewise, time slots 1-15 and 17-31 received from the e1 line are written to the receive slip buffer when it is enabled or directly to the data highway, lead rtdatn when it is bypassed. time slot 16 is treated like the other time slots in reception from the e1 line, being slip buffered, if selected, and placed on rtdatn. the transmitted time slot 16 is treated like the other time slots and taken from the transmit slip buffer or directly from ttdatn or ttaixn if ccs signaling is selected (control bits typ1 and typ0 in register x+134h are both set to 0). time slot 16 is generated by the framer if cas signaling is selected (control bits typ1 and typ0 in register x+134h are not both set to 0). the transmit slip buffer loca- tions are registers x+91h - x+afh (frame 1) and x+b1h - x+cfh (frame 2). locations x+90h and x+b0h contain tfas and tnfas as described above. the receive slip buffer locations are registers x+41h - x+5fh (frame 1) and x+61h - x+7fh (frame 2). locations x+40h and x+60h contain rfas and rnfas as described above. an individual transmit time slot in the buffer can be frozen by writing a 0 to one or more con- trol bits tde1 - tde31 in registers x+e4h - x+e7h; data from the data highways will no longer be written to the selected time slot(s) but the contents of the transmit slip buffer will still be output to the e1 line. an individ- ual receive time slot in the buffer can be frozen by writing a 0 to one or more control bits rde1 - rde31 in reg- isters x+3ch - x+3fh; data from the e1 line will no longer be written to the selected time slot(s) but the contents of the receive slip buffer will still be output to the data highway. the individual time slots in both frames can be accessed by the microprocessor, as well as written by the microprocessor in place of data. this permits the microprocessor to write idle or service codes for one or more framer time slots. please note that both buffer locations (i.e., frame 1 and frame 2) must be written. each framer contains a two-frame slip buffer in both the transmit and receive data directions. either of the slip buffers can be bypassed, if required, in the transmission and data modes only. the slip buffers must be enabled in the mvip and h-mvip/h.100 modes. both the transmit and receive data time slots (1-15 & 17-31 plus 16 for ccs) and the framing time slots (time slot 0) are passed through the slip buffers. the signaling states are buffered in a separate memory location and are not subjected to slips. each buffer is organized as a circular queue two frames in length. if data is arriving faster than it is being removed, the buffer will begin to fill. before the buffer becomes totally full, a controlled slip will occur and one frame of data will be discarded. this is accomplished by moving the write pointer back one frame and overwriting the previous frame that was writ- ten. if the data is being removed faster than it is arriving, the buffer will begin to empty. before the buffer becomes completely empty, a controlled slip occurs in the opposite direction, and a frame of data is added to the buffer. this is accomplished by moving the read pointer back one frame and repeating the last frame read. the transmit or receive slip buffer may be manually toggled by setting the tsr or rsr control bits (bits 4) in control registers x+11ch and x+11bh to a 1, respectively. manual toggling may be used to control delay. the transmit slip buffer is used to absorb low speed jitter in the transmit direction. the transmit slip buffer is enabled by writing a 1 to control bit txsbe (bit 5) in control register x+11ch. when enabled, time slots are written into the transmit slip buffer by the system clock (ttclkn), and read out by the recovered receive clock (rclkn), the system clock (ttclkn), or the local oscillator (bposc). control bits txc1 and txc0 (bits 7 and 6) in register x+11ch select the clock source. the time slots (c = 1-31) from the transmit data bus (ttdatn and /or ttaixn) are written into the slip buffer when their respective enable bits (tdec) in registers x+e4h, x+e5h, x+e6h and x+e7h are written with a 1. if a phase shift between the two clocks is detected, a deletion or repetition of one frame of data occurs by the buffer reaching an almost full or almost empty threshold. a transmit slip is indicated by status bit slip (bit 1) in register x+10h. an associated mask bit mslip, a latched event bit lslip, a performance value pslip and a fault value fslip are all bit 1 in registers x+14h, x+11h, x+12h and x+13h, respectively. the transmit slip buffer detailed status is indicated by reading status bits txs1 and txs0 (bits 7 and 6) in register x+16h, which indicate if a slip has occurred and if it is a repetition, deletion or error. since the slip status bit is shared with the receive slip buffer, when both slip buffers are enabled the status bits rxs1 and rxs0 (bits 7 and 6) in reg- ister x+15h should also be read. a simplified schematic of the transmit slip buffer is shown in figure 50. - 116 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers shutting off the bposc and ttclkn or rtclkn clock signals should be avoided when the slip buffers are enabled in the mvip and h-mvip/h.100 modes since otherwise a constant slip error may result even after the clocks are restored. if this cannot be avoided, then a software reset for that channel should be generated to ensure clearance of the slip error, when the same condition is detected, and the value of the transmit/receive delay register is close to zero (less than 5). figure 50. transmit slip buffer the receive slip buffer is typically used when the receive system clock (rtclkn) is provided from an external source which is accomplished by setting control bit rxcke (bit 7) in register x+11bh to a 0 and control bit rxsbe (bit 5) in the same register to a 1. the receive slip buffer controls the time slot access and retiming, providing a two-frame buffer that is optionally bypassable in the transmission and data modes only. the slip buffer must be enabled in mvip and h-mvip/h.100 modes. time slots from the line interface are written into the slip buffer by the recovered receive clock (rclkn), and read out by the system clock (rtclkn). if a phase shift between the two clocks is detected, a deletion or repetition of one frame of data occurs by the buffer reaching an almost full or almost empty threshold, respectively. the time slots (c = 1 - 31) from the receive line signal are written into the slip buffer when their respective enable bits (rdec) in registers x+3ch, x+3dh, x+3eh and x+3fh are written with a 1. rsis and rsa4s-rsa8s in register x+3bh for time slot 0 are writ- ten with a 1 control the national and international bits as described above. individual time slots can be accessed by the microprocessor, and they can be written by the microprocessor in place of data. when a time slot enable control bit rdec in register locations x+3ch-x+3fh is written with a 0, the content of the two-frame slip buffer location is frozen for that time slot. the microprocessor can write an idle, code word or service code in the location that will be transmitted to the receive data highway. the receive slip buffer data locations rts1-rts31 are x+41h (time slot 1) to x+5fh (time slot 31) for frame 1, and x+61h (time slot 1) to x+7fh (time slot 31) for frame 2. the receive time slot 0 for fas frames and nfas frame are located at x+40h and x+60h respectively. please note that both buffer locations (i.e., frame 1 and frame 2) must be written. a simplified schematic of the receive slip buffer is shown in figure 51. a receive slip is indicated by status bit slip (bit 1) in register x+10h which is shared with the transmit slip as described above. the receive slip buffer status is indicated by reading status bits rxs1 and rxs0 (bits 7 and 6) in register x+15h which indicate if a slip has occurred and if it is a repetition, deletion or error. since the transmit slip buffer slip buffer control 0 1 00 01 10 divide by 256 txsbe (bit 5 in x+11ch) transmit data txc1, txc0 bposc ttclkn rclkn synchronization tsr note: n is the framer number ( 1 - 8 ) and c is the time slot number ( 1-31 ) (bit 4 in x+11ch) ttclkn ttdatn ttfrmn e1fx8 (local oscillator) (control bits, bits 7 and 6 in x+11ch) framer n ttaixn milliwatt idle (regs. x+111h- x+118h) tc1cc- tc0cc 00 01 10 11 tdec (regs. x+e4h - x+e7h) - 117 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers slip status bit is shared with the transmit slip buffer, when both slip buffers are enabled the status bits txs1 and txs0 (bits 7 and 6) in register x+16h should also be read. figure 51. receive slip buffer the receive slip buffer has its read and write pointers available in register x+20h through x+23h and the trans- mit slip buffer has its read and write pointers available in registers x+26h through x+29h. in addition, delay values are available. the value present in status registers rxsbd8 (bit 6) at location x+23h and rxsbd7 - rxsbd0 at location x+24h represents the difference between the receive slip buffer write pointer and read pointer yielding a delay value in increments of 1 bit. this delay value can be read periodically to determine the frequency offset between rclkn and rtclkn. the value present in status register txsbd7-txsbd0 at loca- tion x+25h and txsbd8 (bit 6) in register x+29h represents the difference between the transmit slip buffer write pointer and read pointer, yielding a delay value in increments of 1 bits. slip buffering unframed signals (transmission or data mode only) when control bit ttfm (bit 6) in register x+01h is set to a 1 and txsbe (bit 5) in register x+11ch is set to a 1, the transmit slip buffer is operating on all 256 bits of data present on ttdatn every 125 microseconds, and they are passed unaltered (except for the coder function) to the transmit line side, without frame bits or signaling bits being inserted. ttfrmn, ttsign and ttaixn inputs are ignored. slips caused by clock differences between ttclkn and the transmit line clock source (rclkn or bposc) will be implemented by a repeat or skip of 256 bits, not the payload (time slots 1-15 and 17-31 plus 16 for ccs) as is done when ttfm is set to a 0. when control bit rtfm (bit 7) in register x+01h is set to a 1 and rxsbe (bit 5) in register x+11bh is set to a 1, the receive slip buffer is operating on all 256 bits received from the line and no attempt is made to find frame alignment. the data on rtdatn is unaltered data from the received line except for the decoder function if enabled. data on rtsign and rtfrmn is to be ignored. slips caused by clock differences between rclkn and rtclkn will be implemented by a repeat or skip of all 256 bits, not the payload (time slots 1 - 15 and 17 - 31 plus 16 for ccs) as is done when rtfm is set to a 0. control bit ts0fz (bit 5) in register x+134h must be set to a 1 to permit time slot 0 to be treated as a telephone channel and slip buffered as time slots 1 - 31. receive slip buffer slip buffer control 0 1 rtdatn rsr note: n is the framer number (1 - 8) and c is the time slot number (1 - 31) (bit 4 in x+11bh) rtclkn receive data rtfrmn e1fx8 rxsbe rxcke (bit 7 in x+11bh) rclkn recovered sync (bit 5 in x+11bh) framer n rdec (regs. x+3ch - x+3fh) - 118 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers delay delay through the e1fx8 is a function mainly of the slip buffers, though other factors also influence the amount of delay. the table below gives the typical delay through the framer from line to system and from system to line. the delay numbers are with the slip buffers disabled. the total delay with the slip buffers enabled can be esti- mated by adding the slip buffer delay (8 to 378, see notes 1 and 2). all numbers are in bit times for a clock rate of 2048 khz. note 1: when the framer is reset, the nominal delay is 128 bits through the slip buffer. recenter (control bit rsr or tsr toggled) will cause a slip. note 2: the actual delay value in bits may be determined by reading the value from registers x+24h and bit 6 of x+23h (receive slip buffer) or registers x+25h and bit 6 of x+29h (transmit slip buffer). signaling there are two types of signaling schemes used for the e1 telephone channels: common channel signaling (ccs), and channel associated signaling (cas). common channel signaling, such as ccs no. 7 or isdn d channel, can be assigned to be carried in one or more of the time slots, including time slot 16. the e1fx8 does not process any part of the common channel signaling format. instead, it is passed transparently through the system to the data bus. the clear channel capability for time slot 16 is selected when control bits typ1 and typ0 (bits 7 and 6) in register x+134h are written with 00. time slot 16 for ccs applications may also be switched via the auxiliary port where it can be processed by a device such as the transwitch mchdlc vlsi device. time slot 16 may be used to carry channel associated signaling. the channel associated signaling feature is selected when control bits typ1 and typ0 (bits 7 and 6) in register x+134h are written with a value other than 00. the signaling information is carried as abcd signaling bits that are associated with time slots 1 through 15, and 17 through 31. a sixteen-frame format, referred to as a signaling multiframe, is used to carry the signaling information. please note that the signaling multiframe may be received arbitrarily with respect to the multiframe structure carried in time slot 0. however, time slot 0 multiframe and time slot 16 multiframe are synchronized for transmission. the following table shows the signaling multiframe structure for time slot 16. direction of signal flow rxcp/ txcp overall delay nrz ami/hdb3 rposn/rnrzn to rtdatn rxcp=0 8 12.5 rxcp=1 7 11 ttdatn/ttaixn to tposn/tnrzn txcp=0 5 9 txcp=1 4.5 8.5 framebit 12345678 0 0 000x0yx1x2 1 a1 b1 c1 d1 a16 b16 c16 d16 2 a2 b2 c2 d2 a17 b17 c17 d17 3 a3 b3 c3 d3 a18 b18 c18 d18 4 a4 b4 c4 d4 a19 b19 c19 d19 5 a5 b5 c5 d5 a20 b20 c20 d20 - 119 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers where: ac bc cc dc represents the signaling information associated with the telephone channel number (c = 1-30). channel 1 corresponds to time slot 1, while channel 16 corresponds to time slot 17, since time slot 16 is assigned to carry the signaling information. the y-bit is used for a multiframe alarm indication. a 1 indicates an alarm. the x0, x1 and x2 spare bits are not used, and are normally set to 1. channel associated signaling multiframe alignment time slot 16 may be assigned for channel associated signaling or as a clear channel. different modes of channel associated signaling are selected when control bits typ1 and typ0 (bits 7 and 6) in register x+134h are equal to 01, 10, or 11. when control bits typ1 and typ0 are equal to 00, time slot 16 is designated as a clear channel, and the transmitted path is from the data highway as described above. the selection is common for the receive side of the same framer. the e1fx8 supports two cas multiframe alignment operating modes for each framer: standard, or enhanced. the standard algorithm is selected by writing a 0 to control bit casa (bit 4) in register x+01h. the enhanced algorithm is selected when a 1 is written to the control bit casa. the standard multiframe alignment algorithm is compatible with itu-t recommendation g.732. standard channel associated signaling multiframe align- ment is declared when the e1fx8 detects a 0000 pattern in bits 1 to 4 in time slot 16 and this was preceded by a time slot 16 with a non-zero pattern in bits 1-4. for the enhanced algorithm, multiframe alignment is declared only when the 0000 pattern is found after the previous 15 frames contained a time slot 16 that did not carry the 0000 pattern in bits 1-4. the status bit ts16me (bit 4) in register x+18h is assigned for a multiframe error indication for each framer. a 1 indicates that an error was detected in the 0000 multiframe alignment pattern (bits 1-4 of time slot 16 frame 0). when a 1 is written to control bit eoo16m (bit 1) in register x+03h, a loss of time slot 16 multiframe indi- cation is set when any of the following conditions occurs: - the 4-bit all zero pattern (bits 1-4) in time slot 16 is lost for two consecutive multiframes. - time slot 16 is all zeros for 16 consecutive frames. - basic frame alignment is lost (oof alarm) the time slot 16 loss of multiframe alarm status bit oo16m (bit 2) is in register x+164h. an associated mask bit moo16m, a latched event bit loo16m, a performance value poo16m and a fault value foo16m are all bit 6 a6 b6 c6 d6 a21 b21 c21 d21 7 a7 b7 c7 d7 a22 b22 c22 d22 8 a8 b8 c8 d8 a23 b23 c23 d23 9 a9 b9 c9 d9 a24 b24 c24 d24 10 a10 b10c10d10a25b25c25d25 11 a11 b11c11d11a26b26c26d26 12 a12 b12c12d12a27b27c27d27 13 a13 b13c13d13a28b28c28d28 14 a14 b14c14d14a29b29c29d29 15 a15 b15c15d15a30b30c30d30 framebit 12345678 - 120 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 2 in registers x+166h, x+165h, x+167h and x+168h, respectively. when control bit ts16eic (bit 0) in regis- ter x+00h is set to a 1, status bit oofm will also indicate the alarm. when control bit auty (bit 0) in register x+08h is set to a 1, a loss of time slot 16 multiframe causes the transmitted time slot 16 y-bit (bit 6 of time slot 16 frame 0) to be set to a 1. time slot 16 ais is detected by receiving three or less zeros in each of two consecutive time slot 16 multi- frame periods. if control bit e16ais (bit 0) in register x+05h is set to a 1, status bit ais16 (bit 6) in register x+164h will indicate time slot 16 ais. an associated mask bit mais16, a latched event bit lais16, a perfor- mance value pais16 and a fault value fais16 are all bit 6 in registers x+166h, x+165h, x+167h and x+168h, respectively. when control bit ts16eic (bit 0) in register x+00h is set to a 1, status bit ais will also indicate the alarm. time slot 16 rai is detected if three consecutive received y-bits (bit 6 of time slot 16 frame 0) are set to a 1. if control bit enraiy (bit 0) in register x+04h is set to a 1, status bit rai16 (bit 4) in register x+164h will indi- cate time slot 16 rai. an associated mask bit mrai16, a latched event bit lrai16, a performance value prai16 and a fault value frai16 are all bit 4 in registers x+166h, x+165h, x+167h and x+168h, respec- tively. when control bit ts16eic (bit 0) in register x+00h is set to a 1, status bit rai will also indicate the alarm. channel associated signaling is inserted into time slot 16 of the transmitted frame from the signaling highway via buffer locations. the buffer location for reading the multiframe pattern, spare bits, and multiframe alarm is register x+d0h. the buffer locations for the abcd bits of the signaling channels are registers x+d1h through x+deh. all signaling states (i.e., all 30 abcd signaling bits) can be frozen by writing a 1 to control bit txsfz (bit 0) in register x+134h. the contents of an individual signaling nibble in buffer locations x+d1h through x+deh can also be frozen by writing a 0 to one or more of control bits tse1-tse30 in registers x+ech- x+efh. when a signaling a nibble is frozen, the transmitted signaling state is the value sitting in the buffer at the time bit tsec was set to 0. the microprocessor can write a new signaling state, or a service code, for the frozen nibble to effect trunk conditioning or originate signaling control, for example. frame 0 in the 16-frame multiframe carries the 4-bit multiframe pattern, 3 spare bits, and the remote multi- frame alarm (rai) in the y-bit. the e1fx8 regenerates the 4-bit multiframe alignment pattern. the spare and y-bits from the signaling highway can be read by the microprocessor in register x+d0h (bits 3-0). the y-bit can be set if the receiver detects a time slot 16 out of multiframe alignment as described above. the micro- processor can also generate a remote multiframe alarm by writing a 1 to control bit ts16ye (bit 5) in register x06h. the 3 spare bits, x0, x1 and x2, may be taken from the signaling highway in transmission mode if con- trol bits tx0s, tx1s and tx2s (bits 0, 1 and 2) in register x+e2h are set to a 1. when tx0s, tx1s and tx2s are set to 0, the values stored in location x+d0h (bits 3, 1 and 0). time slot 16 ais may be inserted as all ones in time slot 16 (including the multiframe pattern in frame 0) by setting control bit tais16 (bit 1) in register x+07h to a 1. the following table, which is common to both the receive and transmit sections, lists the states for signaling. typ1 typ0 signaling type 0 0 time slot 16 is assigned as a clear channel (ccs). 0 1 time slot 16 assigned for cas. abcd signaling bits from transmit signaling buffer and to receive signaling buffer. if abcd = 0000 from the transmit signaling highway or stored in the transmit signaling buffer (evaluated after the tsinv function), the value is replaced by abcd = 1111 to prevent mimics of the time slot 16 multiframe alignment pattern. 1 0 time slot 16 assigned for cas. abcd signaling bits from transmit signaling buffer and to receive signaling buffer. 1 1 not used. - 121 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling buffers the receive signaling buffers that are used to interface the e1fx8 to the system are 360 bits in length. the transmit signaling buffers that are used to interface the e1fx8 to the system are 120 bits in length. in the receive direction, the signaling bits are extracted from the data stream and placed in the receive signaling buffer after time slot 16 multiframe alignment is detected as described above. three storage locations are provided for each signaling bit received to permit signaling debouncing to be accomplished under control of control bit sigdb (bit 4) in register x+134h. a simplified schematic of the receive signaling buffer is shown in figure 52. in the transmission mode, eight signaling bits are sent each frame, and all signaling states are sent over the 16 frames. receive signaling bits are clocked out by the system clock (rtclkn), which is sourced by either the system interface or the e1fx8. these bits can be extracted using the receive synchronization signal rtfrmn. in the data, mvip and h-mvip/h.100 modes, all the signaling bits are sent for every time slot every frame (125 microseconds) from the receive signaling buffer by using the system clock (rtclkn) and sync pulse (rtfrmn). figure 52. receive signaling buffer the received signaling bits are stored sequentially in the receive signaling buffer in the order they are received. two temporary rams are provided at locations x+138h through x+146h for ram 1 and x+148h through x+156h for ram 2. signaling ram 1 contains the current value and signaling ram 2 keeps a count of the number of frames the current value and the just received value match. the signaling bits in the receive main or debounced signaling buffer (register locations x+81h through x+8fh) may be read at any time by the micro- processor in order to monitor the signaling states, or written to modify the outgoing values. when signaling debounce is used, the signaling bits are enabled to be stored by control bits rse1-rse30 in registers x+e8h through x+ebh and are written to the active ram 1 first. if the just received signaling nibble matches the value in ram 1, ram 2 for that location is incremented. if the just received signaling nibble does not match the value stored in ram 1 for a specific location, the associated ram 2 location is cleared to 0h. when the value stored in a specific location of ram 2 is equal to or exceeds that value written into debval(3-0) (bits 3-0) of register 0feh, the signaling nibble for that specific location is transferred from ram 1 to the main signaling parallel to serial read address rx signaling main ram data addr write address recovered multiframe synch cpu data cpu addr rtclkn rtfrmn rtsign 4 5 5 7 5 note: n is the framer number (1 - 8) e1fx8 framer n i/o rx signaling active rams data addr in from framing hardware out (debounced) 5 & debounce logic sigdb = 1 0 1 sigien, rxsfz bits rse1-rse30 bits change of signaling indication - 122 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers buffer; this value is used to output on the signaling highway or to be read by the microprocessor. for test pur- poses both active rams are also available to the microprocessor, which is not shown in figure 52. since the buffer is accessed by multiple asynchronous processes, the read and write cycles for the signaling buffer are synchronized to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the signaling debounce is enabled (sigdb = 1), updates by the micro- processor should be preceded by a signaling freeze by setting control bit rxsfz (bit 1) in register x+134h to a 1, which will prevent a debounced value from overwriting the microprocessor value. when a 0 is written into control bit rsec, the signaling buffer for time slot c signaling is frozen. the frozen states will be sent on the sig- naling highway until the rsec bit is written with a 1 or the microprocessor writes a new signaling value to the main ram. the signaling bits in the receive direction are automatically frozen in their present states when loss of signal or loss of synchronization occurs (los, ais, oof or oof16m). a signaling freeze may also be initi- ated manually by writing a 1 to control bit rxsfz. a receive signaling freeze indication is given by unlatched status bit rxsf (bit 1) in register x+17h. transmit signaling buffers a simplified schematic of the transmit signaling buffer is shown in figure 53. transmit signaling bits on the sig- naling lead ttsign are clocked into the transmit signaling buffer using the transmit system clock ttclkn and sync pulse ttfrmn. in the transmission mode, four signaling bits are provided each frame. in the data, mvip and h-mvip/h.100 modes, all signaling bits are written to the tx signaling ram for every channel every other frame (250 microseconds). however, signaling on the signaling highway must be provided every frame. figure 53. transmit signaling buffer the transmit signaling bits from the signaling highway are stored sequentially in the transmit signaling buffer in the order they are received. the signaling bits in the transmit signaling buffer (register locations x+d1h through x+dfh) may be read at any time by the microprocessor in order to monitor the signaling states, or written to modify the outgoing values. since the buffer is accessed by multiple asynchronous processes, the read and write cycles for the signaling buffer are synchronized to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the corresponding signaling serial to parallel write address tx signaling ram data addr read address to framing hardware txsync txfsync cpu data cpu addr ttclkn ttfrmn ttsign 4 5 5 5 5 note: n is the framer number (1 - 8) e1fx8 framer n i/o - 123 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers enable bits tse1- tse30 in register locations x+ech (telephone channels 1-8), x+edh (telephone channels 9 - 16), x+eeh (telephone channels 17 - 24) and x+efh (telephone channels 25-30) are written with a 1, the signaling bits are written into the transmit signaling buffer. for example, a 1 written to control bit tsec enables the signaling bits from the signaling highway for time slot c to be written into the signaling buffer. when a 0 is written into control bit tsec, the signaling buffer for time slot c signaling is frozen. the frozen states will be transmitted until the tsec bit is written with a 1 or the microprocessor writes a new signaling value. a transmit signaling freeze indication occurs when control bit txsfz (bit 0) in register x+134h is written with a 1 (manual freeze). a transmit signaling freeze indication is given by status bit txsf (bit 0) in register x+17h. signaling change of state interrupt a change of signaling state indication and associated interrupt is provided if control bit sigien (bit 3) in regis- ter x+134h is set to a 1. this feature operates on the receive signaling data as is referenced in figure 52. this feature should only be used with signaling debounce in situations where rotary dial addressing is not expected. when sigien is set to a 1 any change in any signaling bit is detected and status bit schg (bit 0) in register x+10h will be set to a 1 momentarily. an associated mask bit mschg, a latched event bit lschg, a perfor- mance value pschg and a fault value fschg are all bit 0 in registers x+14h, x+11h, x+12h and x+13h, respectively. signaling nibble substitution for ais and rai when line side or system side alarms are present, specific signaling codes may be substituted for the signaling abcd nibbles normally used. when control bit rx0aise (bit 7) in register x+03h is set to a 1 and e1 ais, los or oof is detected and enabled by control bits enais, enloof and enlos (bits 7-5) in register x+02h, all the signaling nibbles on signaling highway, rtsign, are replaced with a code written to codeais (bits 3-0) in register 02ch. codeais may be forced to the signaling highway signaling nibbles by setting rt0ais (bit 6) in register x+03h to a 1. this feature may be used to meet itu-t g.732 requirement on the detection of excessive bit error rate as calculated by framing word error counts (see lfbe0 - lfbe9) by setting codeais to fh and setting rt0ais to a 1 on excessive ber. likewise, if rai from the e1 line is detected and control bit rx0rai (bit 5) in register x+03h is set to a 1, all the signaling nibbles on the signaling highway, rtsign, are replaced with a code written to coderai (bits 7-4) in register 02ch. coderai may be forced to the signaling highway signaling nibbles by setting rt0rai (bit 4) in register x+03h to a 1. if ais is detected on the signaling highway (in transmission mode only) by having the ?a? bits set to 1, if con- trol bit tx0aise (bit 1) in register x+06h is set to a 1 and control bit extais (bit 5) in register x+06h is set to a 0, only time slot 16 signaling nibbles transmitted to the e1 line are affected by being replaced with codeais (bits 3-0) in register 02ch. codeais may be forced on time slot 16 signaling nibbles transmitted to the e1 line by setting control bit st0ais (bit 0) in register x+06h to a 1. - 124 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers clocking and synchronization the clocking and synchronization portion of the e1fx8 includes the receive clock configuration, transmit clock synchronization, and the slip buffers for each of the framers. the following table provides a summary of the rtclkn clock operation in the receive direction. * note: control bit rxcke (bit 7) in register x+11bh configures rtclkn as an input or output for each of the framers. in the mvip and h-mvip/h.100 modes, the system clock must be an input. in the transmit direction, the system clock ttclkn and sync pulse ttfrmn are always inputs to the e1fx8. the transmit data input on ttdatn or ttaixn is clocked out of the slip buffer by either the transmit system clock (ttclkn), the local oscillator input (bposc), or the recovered receive clock (rclkn). the clock selec- tion for each framer is controlled by txc1 (bit 7), and txc0 (bit 6) in framer clock control register x+11ch. the local oscillator input (lead bposc) has a nominal frequency of 2.048 mhz and should be accurate to 50 ppm. bposc is the source for the rclkn output when rxcke = 1 and los is detected. the following table provides a summary of the ttclkn clock operation in the transmit direction. clock reference for system applications that require the recovered receive clock, the e1fx8 can provide two reference clocks derived from any of the eight clock inputs (rclkn), when enabled. the recovered receive clock input rclkn that is used to derive the reference clock scout1 is determined by the value written to control bits s1ync2 - s1ync0 (bits 2, 1 and 0) in register 024h. the recovered receive clock that is used to derive the reference clock scout2 is determined by the value written to control bits s2ync2 - s2ync0 (bits 2, 1 and 0) in register 025h. the following table lists the various conditions for enabling/disabling the clock reference signal on the scout1 and scout2 leads. the loss of signal condition can be internally detected in dual unipolar mode when control bit rail (bit 7) in register x+00h is set to a 1 or it can be enabled in the nrz mode through the rscann input lead as described in the line interface selection section above. the s1ctri, s2ctri, s18khz and s28khz control bits are located in registers 024h and 025h. interface mode clock rate sync edge in data/sig edge out comments transmission 2.048 mhz pos. neg. clock and sync pulse may be outputs* in which rtclkn clock is derived from the recovered received clock (rclkn). mvip 2.048 mhz pos. pos. system clock and sync pulse must be inputs. data 2.048 mhz pos. neg. clock and sync pulse may be outputs* in which rtclkn clock is derived from the recovered received clock (rclkn). h-mvip/h.100 16.384 mhz pos. neg. system clock and sync pulse must be inputs. interface mode clock rate sync edge in data/sig edge in comments transmission 2.048 mhz pos. pos. system clock and sync pulse must be inputs. mvip 2.048 mhz pos. neg. system clock and sync pulse must be inputs. data 2.048 mhz pos. pos. system clock and sync pulse must be inputs. h-mvip/h.100 16.384 mhz pos. pos. system clock and sync pulse must be inputs. - 125 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers note: x=don?t care when the 8 khz reference option is chosen, setting control bit synlf (bit 6) in register 00ch to a 1 causes scout1 and scout2 pulses to occur in synchronism with the selected line?s frame pulse as shown in figure 33. for an ami or hdb3 setting of the line decoder by control bit rail (bit 7) in register x+00h set to 1, the 8 khz pulse on scout1 and scout2 is coincident with the fourth bit of a frame if control bit synlf (bit 6) in register 00ch is set to a 1 and control bit rxcp (bit 3) in register x+00h is set to a 0; for rxcp set to a 1, the 8 khz pulse is coincident with the third bit of the frame. for nrz mode (rail set to 0) the pulse is coincident with the first bit of a frame if control bit synlf (bit 6) in register 00ch is set to a 1 and control bit rxcp (bit 3) in register x+00h is set to a 0; for rxcp set to a 1, the 8 khz pulse is coincident with the last bit of the frame. this feature works in framed modes only. control bit bypass (bit 0) in register x+161h when set to a 1 sources the clock after it has been filtered by the dejitter buffer. one-second clock selection the source of the clock used for internal one-second timing functions can be derived from several sources. it should be noted that for proper itu-t g.703 compliance this source should be accurate to 50 ppm. lead sregt, lead bposc, or one of the eight rclkn can be used for the one-second clock source when the shadow register feature or the ds0 remote loopback feature is enabled. when one of the eight rclkn is selected and this lead experiences a loss of signal, the bposc signal is substituted if control bit s1cien (bit 7) in register 00ch is set to a 1. control bits s1ync2-s1ync0 (bits 2, 1 and 0) in register 024h select which of the eight rclkn are to be used for the one-second clock. the table below indicates the various clock selec- tions which are under control of global control bits s1sextb (selects the external source sregt when set to 0) and s1sint (selects one of the internal sources): note: x=don?t care s1ctri s2ctri los(n) (alarm) s1yncen s2yncen s18khz s28khz action 1 x x x scout1/scout2 lead tristated. 0 0 0 1 8 khz reference provided on scout1/scout2. the 8 khz signal is derived from the recovered clock that is selected (rclkn) by con- trol bits s1ync2 - s1ync0/s2ync2 - s2ync0. 0 0 0 0 2048 khz reference provided on scout1/scout2. the 2048 khz signal is derived from the recovered clock that is selected (rclkn) by control bits s1ync2 - s1ync0/s2ync2 - s2ync0. 0 1 0 x scout1/scout2 lead continues to put out clock when los is detected on the selected reference input. 0 1 1 x scout1/scout2 lead is forced low when los is detected on the selected reference input. los (alarm) s1sextb bit 4 reg. 024h s1sint bit 3 reg. 024h action x 0 x lead sregt is selected as the clock source for one-second timing. x 1 0 the 2048 khz clock from lead bposc is divided down to a one-second source. false 1 1 the 2048 khz clock from lead rclkn as selected by control bits s1ync2-s1ync0 is divided down to a one-second source. true 1 1 the 2048 khz clock from lead bposc is divided down to a one-second source if s1cien is set to 1. - 126 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers ais generation and detection two type of frame ais and time slot 16 ais are detected in the received e1 line signal. when control bit enaisi (bit 5) in register 00ch is set to 0, line ais is detected when the received line signal has two or less zeros in each of two consecutive double-frame periods (512 bits each). recovery occurs when each of two consecutive double-frame periods contains three or more zeros after basic frame alignment has been detected. this corresponds to itu-t g.775 recommendations. when control bit enaisi (bit 5) in register 00ch is set to 1, line ais is detected when the received line signal has two or less zeros in each of two consecutive frame periods (256 bits each). recovery occurs when each of two consecutive frame periods contains three or more zeros after basic frame alignment has been detected. this corresponds to isdn applications as recom- mended by itu-t i.431. the status of line ais is given by the status bit ais (bit 6) in register x+10h if control bit enlais (bit 1) in register x+05h is set to a 1. an associated mask bit mais, a latched event bit lais, a per- formance value pais and a fault value fais are all bit 6 in registers x+14h, x+11h, x+12h and x+13h, respectively. in transmission mode ais can cause the ?a? bits on the signaling highway to be set to 1 if control bits enais (bit 7) and enabit (bit 4) in register x+02h are set to 1. similarly in any mode ais can cause all ones on the data highway if control bits enais (bit 7) and endbit (bit 3) in register x+02h are set to 1. an ais in time slot 16 is detected as described above. the status of time slot 16 ais is given by the ais16 status bit (bit 6) in register x+164h if enabled. time slot 16 ais may be included in ais if control bit ts16ec (bit 0) in register x+00h is set to a 1. the e1fx8 can generate e1 line ais (all ones) if control bit txais (bit 7) in register x+06h is set to a 1. line ais may also be generated in transmission mode by setting control bit extais (bit 5) in register x+06h to a 1 and having the a-bits received from the signaling highway, ttsign, set to 1. during a local loopback, ais may be substituted for the transmitted test signal if control bit txlais (bit 6) is set to a 1 while control bit llp (bit 7) is set to a one both in register x+107h. auxiliary pattern generation and detection the auxiliary pattern is an unframed continuous alternating binary ?10? pattern on the e1 line used in isdn applications. the auxiliary pattern is detected when 254 or more alternating binary ?10? patterns are detected in a 250 microsecond period. if control bit enrxauxp (bit 0) in register x+03h is set to a 1, status bit auxp (bit 0) in register x+164h is set to a 1 if the auxiliary pattern is detected. an associated mask bit mauxp, a latched event bit lauxp, a performance value pauxp and a fault value fauxp are all bit 0 in registers x+166h, x+165h, x+167h and x+168h, respectively. to send the auxiliary pattern, set control bit entxauxp (bit 3) in register x+06h to a 1 and an unframed, alternating binary ?10? pattern will be transmitted to the e1 line. hdlc channel this channel is used to send messages at 4 to 20 kbit/s between network elements using any one or a combi- nation of the national bits. this channel uses an hdlc protocol. a hdlc message frame is composed of four parts: an opening flag, the message (which consists of multiple bytes), a two-byte crc-16 frame check sequence, and a closing flag, as shown in figure 54 below. figure 54. hdlc format bit87654321 opening flag01111110 message address and control information crc-16 closing flag01111110 - 127 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the opening and closing flags are represented by a single, unique 8 bit character defined as 01111110, which contains six contiguous ones. to avoid the occurrence of a false flag within the data stream, a zero is inserted (stuffed) after each string of five contiguous ones in the message or crc-16. reception of more than six con- tiguous ones is interpreted as a frame abort sequence. when an abort sequence is received, the remainder of the current frame is ignored and the received portion is discarded as an invalid frame. a two-byte crc-16 frame check sequence is computed across the contents of the message (after the opening flag), and appended to the end of the message. the time between consecutive frames is filled with one or more flags. when two or more flags occur in sequence, they may share the boundary zero between them (011111101111110). operation at either 4, 8, 12, 16 or 20 kbit/s is supported. the bandwidth of the facility data link is normally 4 khz, when sa4 is assigned to carry hdlc messages. control bits sa4 through sa8 (bits 4-0) in register x+0ch when set to a 1 assign the specific national bits to the hdlc controller. the facility data link bandwidth selection is described in the following table. these control bits are also com- mon with the transmit side. a 128-byte fifo is provided in each direction for each framer, which permits many messages to be transmitted and received without having the microprocessor service the fifos. for longer messages interrupts and status information are provided to facilitate fifo servicing by the microprocessor. for both message types, the hdlc link controller performs the following functions: - zero bit stuffing/destuffing (11111 to 111110 /111110 to 11111) - itu-t crc-16 generation/checking (16-bit sequence) - flag generation/detection (01111110) - abort generation/detection (01111111...) - start of frame detection - end of frame detection - fifo overflow and underflow the hdlc receiver is enabled when a 1 is written to control bit ehr (bit 7) in register x+123h. when enabled, the hdlc receiver will remove the stuffed zero bits, search for the opening flag and place the message con- tents in a 128-byte fifo. the hdlc link controller will compute a crc and compare it against the crc that is received. the received crc is not stored in the fifo and is discarded after being received and checked. the receive fifo is monitored for fill level, with maskable interrupts and latched indications provided. bits rxfs1 and rxfs0 (bits 4 and 3) in status register x+0eh indicate when the receive fifo is less than half full, equal to or greater than half full, full and overflowed. an interrupt may also be sent at the end of the message, or when the fifo is half full, using the rhie control bit (bit 6) in register x+123h to control the conditions for which status bits rhis2-rhis0 (bits 7 - 5) in register x+0eh change. thus, when the messages are always expected to be shorter than the maximum fifo depth of 128 bytes, the hdlc link controller will generate an interrupt only on the completion of the message by setting rhie = 0. if mask bits mrhis2-mrhis0 (bits 7-5) in register x+0fh are set to 001, an interrupt will occur when rhis2-rhis0 = 010; event bits lrhis2-lrhis0 (bits 7-5) in register x+0dh hold the latched value. when the messages are expected to exceed the maximum fifo depth of 128 bytes, the controller will generate an interrupt when the fifo is half filled by setting rhie = 1; mask bits mrhis2-mrhis0 should be set to 001, but now the interrupt based on rhis2-rhis0 = 010 will occur both at the end of message and when the fifo reaches half full. this same function may be accom- plished by leaving rhie = 0 and by monitoring the fifo fill level using status bits rxfs1 and rxfs0 to indi- cate fifo fullness. to generate an interrupt from the rxfs1 and rxfs0 status bits, mask bits mrxfs1 and mrxfs0 (bits 4 and 3) in register x+0fh should be set to 00; when the receive fifo reaches half full, event bits lrxfs1 and lrxfs0 (bits 4 and 3) in register x+0dh will be set to 01 and an interrupt will be generated. interrupts from rhis2-rhis0 can be used to indicate message completions only. bits dpt7 - dpt0 in register x+125h provide the number of bytes presently stored in the receive fifo. bits rhis2-rhis0 (bits 7-5) in register x+0eh provide message status and error indications. the hdlc link con- troller will generate a maskable interrupt for start of message detected, valid message received, crc in error, - 128 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers and message aborted. the message bytes are read by the microprocessor at bits rhd7-rhd0 in register x+124h for each framer. bit 0 corresponds to the first bit received in a byte. to facilitate message reception, both a mask register and a latched event register are provided at locations x+0fh and x+0dh, respectively, in like bit positions for status bits rhis2- rhis0 and rxfs1, rxfs0. to accommodate back-to-back messages, a message length register msl6-msl0 (bits 6 through 0) in register x+128h is provided which is loaded at the end of every message (valid received, abort or received with bad crc). when an interrupt occurs indicating a message has been received, msl6-msl0 should be read. the message length along with message status may be queued for processing later. the value in dpt7-dpt0 is not reset at the end of a message. this allows the microprocessor to read out the receive fifo per received message while another message is being received or wait until several messages exist in the fifo before reading them out and processing them. when initializing the hdlc controller, rhd7-rhd0 must be read repeatedly until the depth value in dpt7-dpt0 is zero. it should be noted that messages with bad crc or messages that were aborted must be cleared from the fifo also. the hdlc transmitter is enabled when a 1 is written to control bit eht (bit 7) in register x+126h. when enabled, the hdlc link controller will transmit flags until data is placed in the transmit fifo. up to 128 bytes can be placed in the fifo. the message bytes are written into bits thd7-thd0 in register x+127h. bit 0 cor- responds to the first bit transmitted. the transmit bytes are read from the transmit fifo, zero insertion is per- formed as needed and a 16-bit crc is computed until the end of message is detected. when the last byte of the message is written into the fifo, the microprocessor must set the end of message status bit eom (bit 5) in register x+126h. the computed 16-bit crc will be appended to the end of the message followed by at least one flag before another message is transmitted. when the transmit fifo is emptied without setting the eom bit, the fifo will set an underflow indication in status bits txfs1 and txfs0 (bits 2 and 1) in register x+0eh coded to 11, and an abort character will be transmitted, thereby terminating the message. the transmit hdlc link controller provides latched event bits and maskable interrupt bits related to the transmit fifo status. information such as underflow and fill status is provided by reading status bits txfs1-txfs0 (bits 2 and 1) in register x+0eh and the corresponding latched event bits ltxfs1 - ltxfs0 (bits 2 and 1) in register x+0dh. transmit hdlc fifo service interrupts may be programmed to occur when the transmit fifo is half empty, or when the last byte is sent, by setting control bit thie (bit 3) in register x+126h. for short messages, the entire message may be written into the fifo, and the controller will generate an interrupt, indicated by status bit this (bit 0) in register x+0eh, when the message has been sent. for longer messages, the controller will gen- erate an interrupt when the fifo is ready to accept more data. to facilitate message transmission both a mask register and a latched event register are provided at locations x+0fh and x+0dh, respectively in like bit posi- tions for status bits this and txfs1, txfs0. there are four general types of message transfers, which are described below: transmitting long and short messages, and receiving long and short messages. the difference between the long and short messages is primarily in how the 128-byte fifos are serviced. with many messages, the entire message will fit into the fifos and interrupts will be generated when the end of the message occurs. with longer messages, the mes- sage will not fit into the fifo, and the message will have to be transmitted or received in several segments. since long and short received messages are similar, their processing is described under the same heading. transmit short message to transmit a short message (up to 128 bytes, excluding flags and crc-16), first configure the transmitter to generate an interrupt at the end of message by writing a 0 to control bit thie (bit 3) in register x+126h. then write a 1 to control bit eht (bit 7) in register x+126h to enable the transmitter. the hdlc link controller will continue to transmit flags until data is written into the transmit hdlc fifo. flags are sent in the selected national bits as a continuous idle pattern even when the hdlc controller is not enabled. write the message into the transmit fifo by writing each byte in turn to thd7-thd0 in register x+127h. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred auto- - 129 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers matically into the fifo. after the last byte is written into the fifo, the eom (bit 5) in register x+126h is written with a 1. the transmitter will then begin to send the message bytes until the fifo is empty. since the eom bit was set, the completion of the message will generate an interrupt, if not masked, indicated by the latched sta- tus bit lthis (bit 0) in register x+0dh. this latched status indication indicates that the message is complete or the fifo is empty. after the crc-16 is sent, the hdlc link controller will start to send flags again. transmit long message to transmit a long message (greater than 128 bytes, excluding flags and crc-16), first configure the transmit- ter to generate an interrupt at the half full level of the fifo by writing a 1 to control bit thie (bit 3) in register x+126h. then write a 1 to control bit eht (bit 7) in register x+126h to enable the transmitter. the hdlc link controller will continue to transmit flags until data is written into the transmit hdlc fifo. flags are sent in the selected national bits as a continuous idle pattern even when the hdlc controller is not enabled. write the first 128-byte message segment into the transmit fifo by writing each byte in turn to thd7-thd0 in register x+127h. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred automatically into the fifo. the hdlc link controller will then start to send the message bytes. when the fifo empties to the half full level, the lthis bit (bit 0) in register x+0dh will be latched, and an inter- rupt generated, if the corresponding mask bit mthis (bit 0) in register x+0fh is set to 0. this is an indication for the microprocessor to write another 64 bytes into the transmit hdlc fifo. this process of sending and refilling is repeated, 64 bytes at a time, until the last byte in the message is written into the fifo. this is fol- lowed by writing the eom (bit 5) in register x+126h with a 1. the transmitter continues to send the final mes- sage bytes until the fifo is empty. when the last byte is transmitted and the fifo is empty, the lthis bit will latch while eom=1, indicating completion of the message. after the crc-16 is sent, the hdlc link controller will start to send flags again. the latched event register x+0dh should be cleared before sending the next message to enable the reception of the status of the next transmitted message. status bits txfs1-txfs0 (bits 2-1) in register x+0eh indicate the fill level of the transmit fifo. if a message is to be aborted, setting control bit tab (bit 6) in register x+126h to a 1 will force the abort code 7fh to be transmitted followed by flags and the clearing of the transmit fifo. receive message to receive a message, first configure the receiver to generate an interrupt at the end of message and at the half full level of the fifo by writing a 0 to control bit rhie (bit 6) in register x+123h and writing mask bits mrhis2-mrhis0 (bits 7 - 5) in register x+0fh to 001 and mrxfs1,0 (bits 4 and 3) in register x+0fh to 00. initialize the receive fifo by reading rhd7-0 in register x+124h repeatedly until the fifo is emptied, which is indicated by dpt7-dpt0 = 00h in register x+125h. then enable the receiver by writing a 1 to control bit ehr (bit 7) in register x+123h. the receiver will generate an interrupt when the fifo is half full, as indicated by the latched status bits lrxfs1,0 (bits 4 and 3) in register x+0dh being set to 01 or when an end of message is detected by latched status bits lrhis2-lrhis0 (bits 7 - 5) in register x+0dh being set to 010 for a valid message received (= 011 for a completed message with crc error or = 1xx for an aborted message received). if a half full interrupt is received, the fifo should be emptied. the receive message is read from the fifo by reading the bytes rhd7-rhd0 in register x+124h. bit 0 represents the first bit in the byte to be received. the bytes in rhd7- rhd0 are transferred automatically from the receive fifo. if some time has elapsed since the interrupt, the depth register dpt7-dpt0 may be read to determine the size of the message received so far. if the end of message indication is set, the microprocessor should read the message bytes from rhd7-rhd0 using the message length register msl6-msl0 (bits 6-0) in register x+128h to detect the remaining number of bytes stored in the receive fifo. please note that the message length is updated when the end of message event indication is latched and interrupt generated, and will not be modified until it is read and cleared by the micro- processor or if another completed message is received. the receive fifo must be read for any type of mes- sage termination (good crc, bad crc or abort). - 130 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers several short messages may be left in the receive fifo and read out at a later time. this is accomplished by storing the message length value read from msl6-msl0 and the latched status read from lrhis2-lrhis0 and lrxfs1,0 in a queue. the message boundaries and validity of the messages read from the fifo may be determined from latched status and message length values. global microprocessor controls and alarms the following line level and time slot 0 alarms for each of the eight framers are detected in the e1fx8: loss of signal (los), alarm indication signal (ais), out of frame (oof), remote alarm indication (rai), change of frame alignment (cfa), out of multiframe (oofm), transmit or receive slip (slip) and change of signaling state (schg). these alarms are provided by the status, event and mask registers (registers x+10h, x+11h and x+12h). a second bank of registers covering time slot 16 and miscellaneous alarms is provided for each of the eight framers: time slot 16 ais (ais16), excessive crc-4 error indication (ecrce), time slot 16 rai (rai16), out of time slot 16 multiframe (oo16m) and the auxiliary pattern (auxp). these alarms are pro- vided by the status, event and mask registers (registers x+164h, x+165h and x+166h). control bit ts16eic (bit 0) in register x+00h when set to a 1 permits ais16, rai16 and oo16m to be ?ored? with ais, rai and oofm. in addition, the following hdlc link level alarms are supported by the e1fx8: receive hdlc event and status, transmit hdlc event and status, receive fifo event and status and transmit fifo event and status (registers x+0dh and x+0eh with masks in x+0fh). control of the ds0 remote loopback activate and deacti- vate sequences, and the prbs analyzer generate status and latched event indications for the receipt of a ds0 remote loopback activation request (intermediate and complete), a ds0 remote loopback deactivation request (intermediate and complete), transmit ds0 activation or deactivation sequence complete, and prbs analyzer out of lock (registers x+129h and x+12ah with masks in x+12b) are also provided. to aid in locating signaling change of state sources, sigact7-sigact0 in register x+19h indicates which group(s) of four time slots triggered the interrupt for status bit schg. the latched status event indication (which can also be referred to as a software interrupt indication) for an alarm or condition is latched on either positive transitions, negative transitions, or both transitions. control bits rise (bit 7), and fall (bit 6) in the global configuration register 00bh determine the transitions that cause an event bit to latch for all eight framers, as shown in the following table: the latched event is cleared by writing a 0 to the associated bit position in the latched status indication register. the e1fx8 also provides a global interrupt mask (gim) bit for the microprocessor interrupt lead (int/irq ). when a 1 is written to control bit gim (bit 5) in the global configuration register 00bh, this hardware interrupt indication lead is tristated when a latched indication (event) bit is set. when a 0 is written into the gim bit, the hardware interrupt lead is enabled. when enabled, the polarity of the interrupt lead can be inverted by writing a 1 to control bit ipol (bit 4) in the global configuration register 00bh. rise (bit 7) fall (bit 6) action 00 latched status bit indications in all registers disabled. hardware and software interrupt indications disabled. 1 0 latched status indication sets on positive alarm transition, along with generating a hardware interrupt provided the corresponding mask bit and the global inter- rupt status indication bit gim (bit 5) in register 00bh are both 0. 0 1 latched status indication sets on negative alarm transition, and generates a hardware interrupt provided the corresponding mask bit and the global interrupt mask bit gim (bit 5) in register 00bh are both 0. 11 latched status indication sets on both positive and negative alarm transitions, and generates a hardware interrupt provided the corresponding mask bit and the global interrupt mask bit gim (bit 5) in register 00bh are both 0. - 131 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers besides providing individual unlatched and latched alarm status indications, and interrupt mask bits, on a per framer basis, the e1fx8 provides global interrupt status indication bits, as well as global interrupt mask bits and framer alarm event pointer bits in the global register segment (registers 011h-01ch). a global interrupt status indication bit is set to 1 in registers 011h and 01ah if the same type of alarm occurs in any of the eight framers, provided that the corresponding global mask bit in registers 012h or 01bh is not set to 1 and the e1fx8 is configured to latch on one of or both transitions of the alarm. registers 014h (chl8-1), 016h (chd8- 1), 019h (chr8-1) and 01ch (chs8-1) provide pointers to the specific framer or framers which caused the line or time slot 0 event, hdlc link event, ds0 remote loopback request/prbs out of lock event or time slot 16/ miscellaneous event, respectively, that triggered the interrupt. for example, assuming a loss of signal alarm occurred in framer 1 only, the los alarm will set the los bit (bit 7) in the unlatched register 210h (i.e., x+10h, with x=200 for framer 1). this alarm indication bit will be set to 1 for the duration of the alarm. assuming that control bits rise and fall (bits 7 and 6) in the global configu- ration register 00bh are set to 10 (latched event set on a positive transition), the transition from 0 to 1 of the los alarm will cause the llos bit (bit 7) in register 211h to latch. a hardware interrupt will be generated on lead int/irq if the interrupt mask bit mlos (bit 7) in register 214h is a 0, and the global interrupt mask bit gim (bit 5) in register 00bh is a 0. if either of these bits is set to 1, the hardware interrupt will not occur. in addition, the latched los indication will also cause a global los indication, glos (bit 7) in register 011h. the framer in which the loss of signal alarm was detected can be found by reading bits 7-0 in register 014h. reading the register confirms that the loss of signal alarm occurred in framer 1. the interrupt will be reset by first reading the llos latched alarm bit position (bit 7) in register 211h and then writing a 0 into the bit position. this will also clear the glos indication bit. if the los alarm persists, it will not cause the latched bit position to relatch. the alarm status can be determined by now reading periodically the unlatched status bit (bit 7) in register 210h, until it becomes 0, indicating that recovery has taken place. this clearing sequence may be selected to occur automatically as described below for shadow registers. shadow registers the e1fx8 also provides shadow registers for the alarms of each of the eight framers. the shadow register feature in the e1fx8 is enabled by writing a 1 to the shadow register enable control bit (srgen), bit 3 in the global configuration register 00bh. by applying a pulse at one-second intervals to lead sregt (or selecting a one-second clock from lead bposc or one of the receive line clocks, rclkn, as described above in the clock selections section), an indication bit will be set in register x+12h if the corresponding line alarm occurred at any time in the last one-second interval. in addition, an indication bit will be set in register x+13h if the alarm is active, but the transition to the active state did not occur in the last one-second interval (i.e., the alarm has per- sisted for longer than one-second). the rising edge of the one-second pulse will also reset a latched event bit position in register x+11h independent of the microprocessor. figure 55 illustrates the operation of the shadow registers for a loss of signal (los) alarm for framer 1. the behavior shown in the diagram also applies to the other signal alarms in the same register x+10h (ais, oof, rai, cfa, oofm, slip, and schg) or in register x+164h (ais16, ecrce, rai16, oo16m and auxp). this figure assumes that control bits rise and fall (bits 7 and 6) in the global configuration register 00bh are set to 10 (latched event set on a positive transition only). please note that the los alarm causes a latched sta- tus indication llos (bit 7) in register 211h, and that the latched bit is reset by the rising edge of the selected one-second pulse (either on lead sregt or via leads bposc/rclkn and controls described in the clock selections section). the plos status bit (bit 7) in register 212h is a 1 whenever there is a transition to los during the last one-second interval or los is present at the end of the last one-second interval. the flos sta- tus bit (bit 7) in register 213h is a 1 if the los alarm is active but did not become active during the previous one-second interval. - 132 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 55. shadow register operation in addition, shadow registers have been provided for monitoring the number of line errors that have occurred in one-second intervals. when the shadow register enable control bit (srgen), bit 3 in the global configuration register 00bh, is a 1, the following shadow registers are updated with the count from the previous one-second interval on the rising edges of the one-second pulse provided (either on lead sregt or via leads bposc/ rclkn and controls described in the clock selections section): a 10-bit register for a crc-4 error count, a 10-bit register an e-bit = 0 count, a 10-bit register for sa6 = 00x1, a 10-bit register for sa6 = 001x, a 16-bit reg- ister for a coding violations count, a 15-bit test analyzer out of lock counter, and an 8-bit register for a framing word error count. the rising edge of the one-second pulse also clears the counters that were holding the count for the transfer to the shadow registers. for example, the shadow register for monitoring frame word errors in framer 1 works in the following way. the 8-bit framing word error counter fbe7-fbe0 in register 2fch counts the number of frame word errors over a one-second interval, which is determined by the selected one-second pulse. at the rising edge of the one- second pulse, the count in register 2fch is transferred to the shadow register lfbe7-lfbe0 in location 2fah. the frame bit error counter in register 2fch is cleared at the same instant and it starts the error count for the next one-second interval. at the end of the next one-second interval, the shadow register is updated with the new count. a counter overflow bit fbeo is also provided (bit 7 in register 2fdh), with a corresponding shadow overflow bit lfbeo (bit 7) in register 2fbh. the microprocessor can also clear the counter in register 2fch by writing 00h to it. the shadow register holds its count during a microprocessor read cycle. one-sec. pulse los llos plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (bit 7 in 213h) (bit 7 in 212h) (bit 7 in 211h) (bit 7 in 210h) (input) note 1: for this example, latched events are set only on positive event transitions. note 2: plos = los + llos evaluated at one-second boundaries (where ?+? is a logical or). note 3: flos = los & llos evaluated at one-second boundaries (where ?&? is a logical and, and x is a logical inversion). - 133 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers maintenance to assist in testing, a built-in pseudo random binary sequence (prbs) generator and analyzer blocks are provided on a per e1 basis, framed or unframed. the prbs generator and analyzer supports the 2 15 -1 bit pseudo-random binary sequence which is specified in the itu-t recommendation o.151. in addition the o.151 2 20 -1 (qrss), 2 11 -1 (o.152), and a 2 23 -1 pseudo-random binary sequences are also provided. an optional 32 bit code word may be substituted for the prbs in framed mode only. each e1 framer may select where the prbs generator and analyzer are connected so that both line testing (generator on the transmit side and analyzer on the receive side) and system testing (generator on the receive side and analyzer on the transmit side) can be supported. the output of the analyzer is provided in a per channel register as well as counted in a 16 bit out of lock counter. the prbs may operate in a framed or unframed mode for the entire e1 channel or it may operate over a single or group of time slots to support fractional e1 and per time slot mainte- nance. the e1fx8 also provides a local line loopback (transmit framer looped to receive framer), remote line loopback (receive line signal looped to transmit line), and payload loopback (time slots 1 through 31 from receive line looped back but with a locally generated time slot 0) options for each e1 channel. in addition any one or more received time slot (except time slot 0) may be selected and looped back and transmitted in place of the time slot input from the data highway or any one of the transmit time slots may be substituted for a received time slot. the e1fx8 provides time slot loopback activate and deactivate code detection and generation in support of the ansi t1.231 / t1.403-core standard permitting single person ?trans-atlantic? loopback testing of fractional t1s/e1s using the e1fx8. local line loopback local line loopback for a framer is enabled when a 1 is written to control bit llp (bit 7) in register x+107h. local line loopback connects the transmit path with the receive path in the direction toward the line, as illus- trated in figure 56 below. the loopback is independent of the line interface selected, nrz or dual unipolar (rail). when control bit txlais (bit 6) in register x+107h is written to 1, an ais (all ones signal) is transmitted to the line instead of test data. please note that transmit line ais can be enabled independent of the local loop- back feature. figure 56. local loopback 0 1 ami/ hdb3 codec llp receive line 0 1 txlais 1?s transmit line line interface internal receive data internal transmit data note: bold/dashed lines show paths used for txlais=1 and llp=1. (if rail = 1) dejitter buffer - 134 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers remote line loopback remote line loopback for a framer is enabled when a 1 is written to control bit rlp (bit 5) in register x+107h. remote line loopback connects the receive line data back to the transmitter, as illustrated in figure 57 below. the loopback is performed before the ami/hdb3 codec. the loopback is independent of the line interface selected, nrz or dual unipolar (rail = 1). a dual unipolar loopback will loop back coding violations if they exist. figure 57. remote line loopback bi-directional loopback a bi-directional loopback for a framer is enabled when a 1 is written to both control bits llp (bit 7) and rlp (bit 5) in register x+107h. the bi-directional loopback connects the receive line data back to the transmitter, as illustrated in figure 58 below. the remote half of the loopback is performed before the ami/hdb3 codec. the dejitter buffer is in neither path during this loopback. the loopback is independent of the line interface selected, nrz or dual unipolar (rail = 1). a dual unipolar loopback will loop back coding violations if they exist. figure 58. bi-directional loopback 1 0 rlp internal receive data internal transmit data transmit line receive line line interface note: bold/dashed lines show paths used for rlp=1. ami/ hdb3 codec (if rail = 1) dejitter buffer 1 0 rlp internal receive data internal transmit data transmit line receive line line interface note: bold/dashed lines show paths used for llp=1 and rlp=1. ami/ hdb3 codec (if rail = 1) dejitter buffer 1 0 llp - 135 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot remote loopback the time slot remote loopback feature is enabled when a 0 is written to control bit tsrlop (bit 7) in register x+109h. one or more time slots can be looped back by writing a 1 to the corresponding control bit tsrl32- tsrl1 in registers x+10ah, x+10bh, x+10ch and x+10dh as shown in figure 59. existing transmit data traffic is not affected if the corresponding time slot is not looped. the loopback takes place after the slip buffer and is provided whether the receive slip buffer is enabled or dis- abled. control bits tsrlop and tsrl32- tsrl1 are set to 0 upon a hardware reset. this function requires the presence of ttclkn to operate correctly. since the transmit framer is reading from the receive slip buffer, contentions may occur due to clock asynchronism between the receive and transmit paths; these are addressed by the e1fx8 and may cause a ?slip? to occur on the looped time slot(s) only. unlatched status rtslpp (bit 5) in register x+15h indicates the phase used for remote time slot loopbacks. a change in value of rtslpp indicates that the time slots being looped back were either repeated or skipped for a single frame. figure 59. time slot remote and payload loopbacks payload remote loopback the e1fx8 device provides two payload remote loopback mechanisms; one that essentially skips the received and transmitted framing byte positions but inserts received non-frame time slot bits into transmit non-frame time slot bit opportunities as soon as possible; the other one maintains time slot integrity by utilizing the time slot loopback feature for all 30 or 31 time slots. for the bit-by-bit style mechanism setting control bit plp (bit 4) in register x+107h provides this feature in a way that only the sequence integrity of the payload is kept. a small fifo is provided between the receive and transmit sides of the framer as shown in figure 59 above to account for skipping the receive time slot 0 and inserting the transmit time slot 0. therefore, the framing posi- tion of the outgoing bit stream is changed relative to the payload signals of the incoming bit stream from the line. in order to keep the framing bit and payload relation intact, the e1fx8 also provides a payload remote loopback by enabling all 30 or 31 time slot loopbacks. this function requires the presence of ttclkn to operate cor- rectly. in this way, the transmit data highway selects the data from the receive data payload through the slip buffers via control bits tsrl32 - tsrl1 in registers x+10ah, x+10bh, x+10ch and x+10dh all being set to a 1 and control bit tsrlop (bit 7) in register x+109h set to a 0 which permits received time slot data to be mapped to transmit time slot position for n = 1 through 32 as shown in figure 59 above. 0 1 to/from line interface receive framer receive signaling receive data tsrlop= 0 & (tsrl32 - tsrl1) receive line interface receive line transmit line transmit data transmit signaling transmit framer transmit line interface from tx slip buffer receive slip & signaling buffer 0 1 fifo (32 bit) plp = 1 - 136 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot local loopback the time slot local loopback feature is enabled when a 1 is written to control bit tsllp (bit 1) in register x+109h. one or more time slots can be looped back by writing a 1 to the corresponding control bit tsll32- tsll1 in registers x+12dh, x+12eh, x+12fh and x+130h as shown in figure 60. existing receive data traf- fic is not affected if the corresponding time slot is not looped. the loopback takes place after the transmit slip buffer and is provided whether the transmit slip buffer is enabled or disabled. control bits tsllp and tsll32-tsll1 are set to 0 upon a hardware reset. this function requires the presence of rtclkn to operate correctly. since the receive framer is reading from the transmit slip buffer, contentions may occur due to clock asynchronism between the receive and transmit paths; these are addressed by the e1fx8 and may cause a ?slip? to occur on the looped time slot(s) only. unlatched status ltslpp (bit 5) in register x+16h indicates the phase used for remote time slot loopbacks. a change in value of ltslpp indicates that the time slots being looped back were either repeated or skipped for a single frame. figure 60. time slot local loopback ds0 remote loopback the ds0 fractional channel loopback requirement is specified in ansi document t1.403-1998, annex b. by definition, remote loopback is the transmission of remote loopback sequence by the local framer to the distant framer. the ds0 fractional channel loopback can involve one or more time slots which may or may not be contiguous but the time slots must all be 64 kbit/s. the intent is to provide single person loopback capability for nx 64 kbit/s channels that pass through a gateway exchange whether they are framed by a t1 framer such as the t1fx8 or an e1 framer such as the e1fx8. figure 61 is a simplified diagram of the code sequence genera- tor. the sequence starting point and ending point in the sequence is arbitrary. figure 61. ds0 remote loopback code sequence generator 0 1 to/from line interface receive framer receive signaling receive data tsllp= 1 & (tsll32 - tsll1) receive line interface receive line transmit line transmit data transmit signaling transmit line interface receive slip & signaling buffer transmit framer transmit slip & signaling buffer 0 = activation 1 = deactivation xor xor ff ff ff ff ff ff ff x7 x6 x5 x4 x3 x2 x1 - 137 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers to activate the ds0 remote loopback feature at the distant end, the loopback activation code for one or more time slots is transmitted for a period of not less than 2 seconds. this will followed by the transmission of an all ones pattern for not less than 2 seconds. the responding end (i.e. distant end) should activate a loopback within the two-second interval immediately following the end of the loopback activation code sequence. to deactivate ds0 at the distant end, the loopback deactivation code is transmitted for a period of not less than 2 seconds, followed by transmission of an all ones pattern for not less than 2 seconds. the responding end should deactivate a loopback within the two-second interval immediately following the end of the loopback deactivation code sequence. for the purpose of either sending the ds0 loopback sequences or receiving them, the ds0 channel functional- ity and capacity must be taken into consideration. all the ds0s in a fractional group must be 64 kbit/s clear channels to permit functional transparency with the e1 environment. it is also expected that alternate digit inversion, zero code suppression and echo cancellation are not present on the path under test. for t1 facili- ties that do not support clear channel capability, it is assumed that the method of alternating ds0s of a fraction with all ones ds0s as recommended in ansi t1.403 annex b is utilized. ds0 loopback activate and deactivate generation in the transmit direction, the remote loopback feature for a fractional channel is configured by writing a 1 to one or more control bits tsrl32-tsrl1 in registers x+10ah through x+10dh when control bit tsrlop (bit 7) in register x+109h is a 1. control bit tsrlop enables the tsrl32-tsrl1 bits to be used for the remote loop- back generation feature. writing a 0 to control bit tsrlop enables the tsrl32-tsrl1 control bits to be used for time slot remote loopback as described above. the tsrl32-tsrl1 control bits select the time slots that define the fractional channel. this approach enables the transmit side to be either configured for sending the remote loopback sequence or enabling a remote time slot loopback locally, but not both configurations at the same time. the remote loopback feature requires the one-second feature to be available (sregt lead, bposc lead or selected rclkn) in order for this feature to function. the transmission of the sequence is locked to nearest starting location of the one-second pulse. the following table reflects the operation of the control bits associated with this feature. control bit ds0da (bit 6) in register x+109h when set to a 0 selects the activation sequence and when set to 1 selects the deactiva- tion sequence. control bit trdslp (bit 5) in register x+109h when set to a 1 initiates the four-second sequence selected by ds0da to be transmitted on only those ds0s selected by tsrl32-tsrl1. note: tsrlop = 1 ds0 remote loopback control ds0da trdslp action 00 ds0 remote loopback feature is disabled, ds0 remote loopback feature is configured for activa- tion pattern but no action taken. 10 ds0 remote loopback feature is disabled, ds0 remote loopback feature is configured for deacti- vation pattern but no action taken. 01 ds0 remote loopback feature activation pattern is sent for the time slots selected (tsrl32- tsrl1). the starting point of the ds0 remote loopback activation sequence can be arbitrary. 11 to send the deactivation pattern, the microprocessor must first write a 0 to the trdslp bit fol- lowed by a 1. the ds0 remote loopback feature deactivation pattern is sent for the ds0 channels selected (tsrl32- tsrl1). - 138 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the completion of the four-second transmit ds0 sequence is indicated by unlatched status bit ds0txc (bit 4) in register x+129h, and latched status indication lds0txc (bit 4) in register x+12ah. please note that the unlatched bit position is a momentary indication. the latched bit is set on positive transitions only. assuming the corresponding mask bit mds0txc (bit 4) in register x+12bh is set to 0, a global indication gds0tc (bit 3) in global register 017h occurs along with an interrupt indication if global control bit gmds0tc (bit 3) in register 018h is set to 0. the microprocessor upon reading the global indication status bit gds0tc should next read the framer pointer register chr8-chr1 at location 019h to determine the framer which has completed the transmission of the sequence. after reading the latched indication (lds0txc - ds0 transmit complete) to indicate that the trans- mission of the sequence is indeed complete, the microprocessor needs to write a 0 to the latched status to clear it. the microprocessor can now write a new time slot in which the send the activate code, or leave the time slot the same for sending the deactivate code. a new sequence cannot be transmitted until control bit trdslp is first written by a 0 followed by a 1. please note, it is the responsibility of the user not to write a new time slot location before the sequence is com- pleted, because the sequence will be transmitted over the new time slot selection and not the old location. monitoring for ansi ds0 remote loopback codes from the network the receive side framer can monitor the time slots that have been designated by the microprocessor as a frac- tional channel. the standard (ansi t1.403-1998) does not specify activation/deactivation detection parame- ters other than that there be a two-second transition period which corresponds to 2 seconds of all ones. the e1fx8 provides the capability of monitoring a single fractional channel at one time. the microprocessor writes the time slots that are to be monitored in control bits tsll32-tsll1 in registers x+12dh through x+130h for the activate/deactivate sequence. control bit tsrlop (bit 7) in register x+109h must be written with a 0 to enable the tsrl32-tsrl1 control bits in registers x+10ah through x+10dh to be used for local loopback upon detection of an activate/deactivate sequence. please note that when control bit tsrlop is writ- ten with a 1, the framer is configured for sending remote loopback, not receiving it, nor being in local loopback. the ds0 remote loopback monitor feature is enabled when control bit rlpen (bit 0) in register x+109h is a 1. the prbs repeated sequence (which is repeated every 128 bits) is monitored for n frames after lock is acquired. the value of n is programmable from 1 to 256 frames (32 ms), by writing the binary value to control bits srtt7-srtt0 in register x+12ch. the value 0 is not valid. an indication of a remote loopback request and release is given by both intermediate unlatched status, mask control, and latched status bits intact, mintact, lintact (bit 3) in registers x+129h, x+12bh and x+12ah respectively and intdct, mintdct, lintdct (bit 2) in registers x+129h, x+12bh and x+12ah respectively which are activated as soon as the activate or deactivate prbs pattern is received for the number of frames indicated by control bits srtt7-srtt0 in register x+12ch. latched status bits lds0act and lds0dct (bits 7 and 6) in register x+12ah are set after the complete prbs sequence is received followed by the all ones pattern. lds0act and lds0dct do not change state until after two frames of continuous ones are received in the monitored fraction in the two-second all ones interval after the two-second activate/deactivate sequence is received. the intermediate indications linact and lindct are to be used when more than one fraction per e1 is to be monitored simultaneously; the microprocessor can update the control bits tsll32-tsll1 (registers x+12dh through x+130h) in a round robin fashion monitoring lintact and lintdct until a request in progress is detected, at which point the control bits tsll32-tsll1 are to be left unchanged until lds0act or lds0dct indicates a complete sequence. there are also unlatched bits ds0act and ds0dct (bits 7 and 6) in register x+129h associated with the latched bits. thus, a valid indication is detected internally, and the acti- vate/deactivate indication is only given at the start of the two-second action time. this is an indication to the microprocessor that a sequence has been detected. the interrupt mask bits are defined as mdact and mddct (bits 7 and 6) in register x+12bh. a global indication is given by status bit gds0rs (bit 7) in register 017h for the activate sequence, and status bit gds0dc (bit 6) in register 017h for the deactivate sequence. a global indication of the intermediate results - 139 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers is given by gintact (bit 3) in register 017h for the activate prbs pattern and by gintdct (bit 2) in register 017h for the deactivate prbs pattern. these status bits are the logical or of a valid ds0 remote loopback acti- vate prbs pattern, deactivate prbs pattern, activation request or deactivation request from the 8 framers. the microprocessor upon reading the global indications should also read the channel pointer, chr8-chr1 in register 019h, to determine which of the 8 framers was requesting a ds0 remote loopback activation or a deactivation request. the microprocessor upon reading the framer n status bits lds0act and lds0dct, may either set or reset the ds0 local loopback control bits tsrl32-tsrl1 in registers x+10ah through x+10dh accordingly, as deter- mined by the channel selected by control bits tsll32-tsll1. please note that it is the responsibility of the user to read the latched indications and take the appropriate action. if the microprocessor does not read the status bits, a new activate or deactivate sequence cannot be detected. the microprocessor should not perform a new channel selection until the activate or deactivate indication is cleared. prbs generator and analyzer the e1fx8 provides the ability to separately generate a pseudo-random bit pattern or to detect a pseudo-ran- dom bit pattern on a per e1 basis or on a nxtime slot basis. a common generator/ analyzer pair is used for both e1 and nxtime slot functions. e1 test generation and analysis both a remote and local prbs test can be performed. to perform the remote prbs test writing a 1 to control bit inprbs (bit 0) in register x+106h enables the framer to transmit a framed or unframed e1 prbs pattern to the e1 line; control bit sinprbs (bit 0) in register x+107h must be set to a 0. writing a 1 to control bit prbre (bit 1) in register x+106h enables the analyzer to monitor the entire e1 received bit stream for a lock status (prbs errors); control bit sprbre (bit 1) in register x+107h must be set to a 0. control bit ttfm, transmit transparent mode, (bit 6) in register x+01h determines if the prbs pattern is to be transmitted framed or unframed. control bit rtfm, receive transparent mode, (bit 7) in register x+01h determines if the prbs pat- tern is to be received framed or unframed. enabling framing permits the prbs pattern to be overwritten with the frame bits at the transmit framer an allows the frame bit positions to be ignored (interpreted as ?don?t care?) at the receive framer. to run a prbs pattern over just the payload, which holds the pattern while the framing bit is inserted and removes the frame bits for analysis, the ds0 feature described below is to be used. to perform the local prbs test writing, a 1 to control bit sinprbs (bit 0) in register x+107h enables the e1fx8 to transmit an unframed e1 prbs pattern to the receive data highway, rtdatn; control bit inprbs (bit 0) in register x+106h must be set to a 0. writing a 1 to control bit sprbre (bit 1) in register x+107h enables the analyzer to monitor the e1 stream received at the input to the transmit slip buffer for a lock status (prbs errors); con- trol bit prbre (bit 1) in register x+106h must be set to a 0. the e1fx8 provides the ability to select one of four prbs patterns; either a 2 11 -1 pattern as defined in itu-t o.152, a 2 23 -1 pattern as defined in itu-t o.151, a 2 15 -1 pattern as defined in itu-t o.151, and ansi t1m1.3-005r1 (april 1993) or the 2 20 -1 qrss pattern as defined in t1m1.3-005r1 (april 1993), itu-t o.151 and ansi t1.403-1995/1997 can be selected. control bits ttprn2, tprn1 and tprn0 (bits 4, 3 and 2) in register x+109h select the particular test pattern to be sent and/or received; tprn1 and tprn0 = 11 is not valid for a full e1 test pattern generation. the prbs and test word analyzer provides an out of lock indication via status bit tplol (bit 5) in register x+129h which is latched in ltplol (bit 5) in register x+12ah. the indication is valid when the mode of the received signal and analyzer match (for framed or unframed). a global status bit gdsotp (bit 5) in register 017h indicates if any of the eight framers has a latched out of lock event. an activity bit per framer is provided by status bits chr1-chr8 in register 019h. the global status and activity bits are cleared by writing a 0 to all of the set ltpol bits. a mask bit mtplol (bit 5) in register x+12ah prevents an interrupt from being gener- ated if set to a 1. the interrupt caused by an out of lock condition can also be masked by setting control bit - 140 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers gmds0tp (bit 5) in register 018h to a 1. a 16 bit error counter is provided which counts out of lock events which is designated testp14-testp0 in registers x+159h and x+15ah with testpo (bit 7) in register x+15ah being the most significant bit or overflow indicator. a latched value ltestp14-ltestp0 with ltestpo in registers x+157h and x+158h being the most significant bit or overflow indicator is also provided which is updated on a one-second basis along with the other performance counters. this feature provides a simple error rate detector for an e1line or payload. for applications of code word testing, such as placing a pattern in every time slot or group of time slots, the time slot test generator analyzer described below may be used. time slot test generation the e1fx8 supports the ability to generate a time slot prbs pattern or a test pattern for each of the framers. with the wide variety of time slot loopbacks available, most any board level, system level or network level test can be supported. this feature is provided in addition to the e1 level test pattern generator and analyzer, and functions the same at the individual time slot or nx time slot level. the receive side is capable of monitoring the data stream for the prbs pattern or test pattern for an out of lock status, and can count the number of out of lock times. the time slot test generator uses the same control bits, tsrl32-tsrl1 in registers x+10ah through x+10dh that are used for selecting the time slots which are also used for sending the activate/deactivate ds0 remote loopback sequence. the time slot test generator also uses tsll32-tsll1 in register x+12dh through x+130h which are used to monitor ds0 loopbacks for sending system side patterns. the ability to transmit a time slot is valid when control bit tsrlop (bit 7) in register x+109h is a 1. the ability to generate a time slot test sequence is disabled when control bit tsrlop is a 0. the type of time slot test sequence that is generated depends on the values of control bits tprn2, tprn1 and tprn0 (bits 4, 3 and 2) in register x+109h, as shown in the following table (where x=don?t care). the time slot test pattern selected by the control bits specified above is transmitted to the e1 line when control bit sprn (bit 3) in register x+131h is written with a 1 for the time slots selected by control bits tsrl32- tsrl1 in registers x+10ah through x+10dh. the time slot test pattern selected by the control bits specified above is transmitted to the system side on rtdatn when control bit ssprn (bit 1) in register x+131h is writ- ten with a 1 for the time slots selected by control bits tsll32- tsll1 in registers x+12dh through x+130h. the various insertion possibilities are shown in figure 62 below. please note that the ability to send the ds0 remote loopback has a higher priority than sending the time slot test pattern. thus, if control bit trdslp is written with a 1, the ability to send a test pattern is disabled until the four-second sequence is completed. e1/ time slot test pattern selection tprn2 tprn1 trrn0 action x00 not used 001 qrss pattern (2 20 -1) pattern defined in t1m1.3-005r1 (april 1993), itu-t o.151 and ansi t1.403-1998, 1997 010 prbs 2 15 -1 pattern defined in itu-t o.151, and t1m1.3-005r1 (april 1993) x11 register test word (for time slot applications only) 101 prbs 2 11 -1 pattern defined in itu-t o.152 110 prbs 2 23 -1 pattern defined in itu-t o.151 - 141 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot test analyzer the time slot test analyzer is enabled to monitor the output of the line decoder when control bit rtpae (bit 2) in register x+131h is a 1. the time slot test analyzer is provided as a bridging function in addition to the cir- cuit that is used to monitor the ds0 remote loopback sequence. the microprocessor writes the time slots that are to be monitored for the test pattern in control bits tsll32-tsll1 in registers x+12dh through x+130h. please note that these bits are also used to select the time slots for the ds0 remote loopback activate and deactivate codes. the ability to monitor for a test pattern is independent of control bit tsrlop. the time slot test analyzer is enabled to monitor the input of the transmit slip buffer when control bit srtpae (bit 0) in register x+131h is a 1. the time slot test analyzer is provided as a bridging function. the micropro- cessor writes the time slots that are to be monitored for the test pattern in control bits tsrl32-tsrl1 in regis- ters x+10ah through x+10dh. when enabled, the test pattern that is to be monitored depends on the setting of the test pattern selection bits tprn2, tprn1, tprn0, (bits 4, 3 and 2) in register x+109h. please note that the transmitter must comply with the receiver for both the test pattern selected for proper operation when two different e1 ports are used. by the appropriate placement of the time slot analyzer and generator a variety of testing possibilities exist. the various insertion possibilities are shown in figure 62 below. when tprn1 and tprn0 are set to 11, the test word as defined in registers x+15bh through x+15eh is selected. this allows a mechanism by which the microprocessor slip buffer write option can be used as a test pattern generator; for example using the receive slip buffer to write a test word, the entire path through an application can be used to carry the test pattern which can then arrive at the transmit data highway of a e1fx8; by placing the e1fx8 in local loopback, the time slot test analyzer can verify the integrity of the path. the time slot test analyzer can also be used to monitor for network generated codes (e.g., idle). the prbs and test word analyzer provides an out of lock indication via status bit tplol (bit 5) in register x+129h which is latched in ltplol (bit 5) in register x+12ah. the indication is valid when the mode of the received signal and analyzer match (for framed or unframed). a global status bit gdsotp (bit 5) in register 017h indicates if any of the eight framers has a latched out of lock event. an activity bit per framer is provided by status bits chr1-chr8 in register 019h. the global status and activity bits are cleared by writing a 0 to all of the set ltpol bits. a mask bit mtplol (bit 5) in register x+12ah prevents an interrupt from being gener- ated if set to a 1. the interrupt caused by an out of lock condition can also be masked by setting control bit gmds0tp (bit 5) in register 018h to a 1. a 16 bit error counter is provided which counts out of lock events which is designated by testp14-testp0 in registers x+159h and x+15ah with testpo (bit 7) in register x+15ah being the most significant bit or overflow indicator. a latched value ltestp14-ltestp0 with ltestpo in registers x+157h and x+158h being the most significant bit or overflow indicator is also provided which is updated on a one-second basis along with the other performance counters. - 142 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 62. prbs/ code word generator/ analyzer options with loopbacks the following table lists the test features supported. please refer to figure 62 for the paths under test. loopback modes with prbs/ code word for the e1fx8 loopback type description external internal generator analyzer framed prbs remote e1 prbs generator through tx slip buffer, coder, line tx to rx or local loop and decoder to prbs analyzer. loop exter- nal line at local liu or at far end. llp = 1 inprbs = 1 ttfm = 0 prbre = 1 rtfm = 0 e1 line e1 line ami/hdb3 coder ami/hdb3 decoder transmit slip buffer receive slip buffer rtdatn ttaixn ttdatn prbs gen. ds0 lpbk analyzer code word analyzer 1 prbs analyzer code word generator 2 code word analyzer 2 code word generator 1 idle milliwatt receive transmit time slot 0 & 16 ds0 lpbk generator plp=1 rlpen & tslln = 1 rtpae & tslln = 1 ssprn & tslln = 1 sprn & tsrln = 1 tsrlop, trdslp & tsrln = 1, ds0da tsrlop = 0 & tsrln = 1 fifo tsrln = 1 llp = 1 rlp = 1 & llp = 1 rlp = 1 & llp = 0 sinprbs or inprbs or sprn & tsrln = 1 sprbre or srtpae & tsrln = 1 prbre or rtpae & tslln = 1 rxsbe = 0 txsbe = 0 tsllp = 1 & tslln = 1 ssprn & tslln = 1 srtpae & buffer dejitter llp = 1 & txlais = 1 ais - 143 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers unframed prbs remote e1 prbs generator through tx slip buffer, coder, line tx to rx or local loop and decoder to prbs analyzer. loop exter- nal line at local liu or at far end. llp = 1 inprbs = 1 ttfm = 1 prbre = 1 rtfm = 1 time slot remote prbs prbs generator through tx slip buffer, coder, line tx to rx or local loop and decoder to prbs analyzer. loop exter- nal line at local liu or at far end. llp = 1 sprn = 1 tsrln = 1 for all time slots selected ttfm = 0 tprn2-0 selects prbs rtpae = 1 tslln = 1 for all time slots selected rtfm = 0 tprn2-0 selects prbs time slot remote code word code word generator (1) through coder, line tx to rx or local loop and decoder to code word analyzer (1). loop exter- nal line at local liu or at far end. llp = 1 sprn = 1 tsrln = 1 for all time slots selected ttfm = 0 tprn2-0=x11 rtpae = 1 tslln = 1 for all time slots selected rtfm = 0 tprn2-0=x11 local e1 prbs all 32 time slots prbs generator through rx slip buffer, rtdatn to ttdatn to prbs analyzer loop rtdatn to ttdatn sinprbs = 1 tprn2-0 selects prbs sprbre = 1 tprn2-0 selects prbs time slot local prbs prbs generator through rx slip buffer, rtdatn to ttdatn to prbs analyzer loop rtdatn to ttdatn ssprn = 1 tslln = 1 for all time slots selected tprn2-0 selects prbs srtpae = 1 tsrln = 1 for all time slots selected tprn2-0 selects prbs time slot local code word code word generator (2) to rtdatn to ttdatn to code word analyzer (2) loop rtdatn to ttdatn ssprn = 1 tslln = 1 for all time slots selected tprn2-0=x11 srtpae = 1 tsrln = 1 for all time slots selected tprn2-0=x11 board test e1 prbs framed prbs generator through rx slip buffer, rtdatn looped to ttdatn to tx slip buffer, to coder, line tx to rx or local loopback, to decoder, to prbs ana- lyzer loop rtdatn to ttdatn loop tx line to rx line at local liu or at far end. llp = 1 sinprbs = 1 ttfm = 0 tprn2-0 selects prbs prbre = 1 rtfm = 0 tprn2-0 selects prbs loopback modes with prbs/ code word for the e1fx8 loopback type description external internal generator analyzer - 144 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers the following are highest to lowest priority for loopbacks etc.: e1 prbs (highest), time slot remote loop- back, ds0 activate/deactivate, prbs or code word insertion, digital milliwatt/ idle word and normal data. high impedance test mode the e1fx8 provides a lead to tristate all output drivers (except lead tbdo) to facilitate board testing. a low placed on lead highz provides this function. board test e1 prbs unframed prbs generator through rx slip buffer, rtdatn looped to ttdatn to tx slip buffer, to coder, line tx to rx or local loopback, to decoder, to prbs ana- lyzer loop rtdatn to ttdatn loop tx line to rx line at local liu or at far end. llp = 1 sinprbs = 1 ttfm = 1 tprn2-0 selects prbs prbre = 1 rtfm = 1 tprn2-0 selects prbs board test prbs time slot prbs generator through rx slip buffer, rtdatn looped to ttdatn to tx slip buffer, to coder, line tx to rx or local loopback, to decoder, to prbs ana- lyzer loop rtdatn to ttdatn loop tx line to rx line at local liu or at far end. llp = 1 ssprn = 1 ttfm = 0 tslln = 1 for all time slots selected tprn2-0 selects prbs rtpae = 1 rtfm = 0 tslln = 1 for all time slots selected tprn2-0 selects prbs board test code word time slot code word generator to rtdatn looped to ttdatn to tx slip buffer, to coder, line tx to rx or local loopback, to decoder, to code word analyzer loop rtdatn to ttdatn loop tx line to rx line at local liu or at far end. llp = 1 ssprn = 1 ttfm = 0 tslln = 1 for all time slots selected tprn2-0=x11 rtpae = 1 rtfm = 0 tslln = 1 for all time slots selected tprn2-0=x11 self test prbs prbs generator through rx slip buffer, remote time slot loop- back to coder local loop- back to decoder, to prbs analyzer llp = 1 tsrlop = 0 tsrln = 1 for all time slots selected ssprn = 1 tslln = 1 for all time slots selected tprn2-0 selects prbs rtpae = 1 tslln = 1 for all time slots selected tprn2-0 selects prbs loopback modes with prbs/ code word for the e1fx8 loopback type description external internal generator analyzer - 145 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers e1 tandem framing monitoring function when control bit bpcrc4 (bit 7) in register x+08h is set to a 1, the signal present on rposn/rnrzn and rnegn is looped to the transmit framer for output on tposn/tnrzn and tnegn unaltered except for dejit- tering if the dejitter buffer is enabled, with any of the sa4-sa8 bits updated from local sources and with the crc-4 updated only to account for the new sa4-sa8 bits. control bits sa4up through sa8up (bits 6-2) in reg- ister x+08h when set to 1 select a local source for the national bits sa4 - sa8. the local source can be the hdlc controller (as selected by control bits sa4-sa8; bits 4-0 in register x+0ch), the transmit signaling high- way / transmit slip buffer (as selected by control bit bnal; bit 5 in register x+122h set to a 1 and control bits tsa4s-tsa8s; bits 4-0 in register x+e3h) or the transmit sa4-sa8 code registers xsa47-xsa40 through xsa87-xsa80 in registers x+169h through x+16dh. the crc-4 update is only done for the specific bits selected by sa4up through sa8up and follows the itu-t g.706 (1995) annex c recommendations. figure 63 provides a functional overview of the e1 tandem monitoring function. for example, an e1 line can be moni- tored for alarms and the entire e1 signal received can be retransmitted except for sa4 and sa5 with sa4 sourced from the code register xsa47-xsa40 for a g.704 synchronization code and sa5 sourced from the hdlc controller. only sa4 and sa5 bits are replaced (sa4up = 1 and sa5up = 1) and the crc-4 for each sub-multiframe is updated to account for the changes introduced by sa4 and sa5. if bit errors have been intro- duced along the way, end-to-end crc-4 checking will catch them and report block errors via the e-bits. for bi- directional performance monitoring and sa4-sa8 insertion, two e1 channels are required. figure 63. tandem frame monitoring with national bit insertion auxiliary port for system applications that need to support isdn pri, isdn bri (multiplexed) or itu g.964 v5.1 functional- ity, an auxiliary port is provided with 32 transmit and 32 receive 64 kbit/s time slots, each individually program- mable to any receive or any transmit time slot (1 to 31) to or from any of the eight e1 framer channels on either the line or system side. limited concatenation functionality is supplied if all time slots are contiguous. setting control bit concaten (bit 4) in register 037h to a 1 enables the concatenation capability for frame n (2 to 31) contiguous time slots to be sourced from a single e1 channel (same direction) and sent out the radat lead as contiguous time slots or sourced from the tadat lead and sent to a single e1 channel (same direction) as con- tiguous time slots. such connections will maintain correct byte sequence frame to frame and any slips to account for clock differences between the auxiliary port and the e1 channel will affect all time slots equally. to/from line interface receive framer sa4 - sa8 to local reg. & receive line interface receive line transmit line sa4 - sa8 local sa4 - sa8 reg. crc-4 update transmit line interface from tx sig. hwy receive slip & signaling buffer 1 0 sa4up - sa8up & bpcrc4 = 1 & to rx sig. hwy receive rx & tx hdlc dejitter buffer - 146 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers each connection is passed through a fifo function with independent depth control to account for line side or system side clock differences to the auxiliary port clock. buffering is provided by this block to match this block?s clock with the 16 transmit e1 and the 16 receive e1 line clock domains. for data output from this port on radat lead clock and frame reference, raclk and rasync, may be an input or an output which is either derived from bposc lead or from either of the reference clock selection outputs. control bits racksel and radirsel (bits 1 and 0) in register 037h determine the direction of the raclk and rasync signals and whether bposc or a selected receive line is used as a clock source when these signals are outputs. input data, clock and frame are provided by input leads tadat, taclk, and tasync. control bits tacksel and tadirsel (bits 3 and 2) in register 037h determine the direction of the taclk and tasync signals and whether bposc or a selected receive line is used as a clock source when these signals are outputs. figure 64 below shows the basic block diagram of the auxiliary port and how it is connected to each of the 8 channel blocks. the tx data selection logic block operates off of the per framer channel timing and controls the insertion of time slots into the receive path or the transmit path. control bits rdir31 through rdir0 in reg- isters 038h through 03bh select which side of the framer each time slot for the receive auxiliary path is sourced; a 0 selects the decoder output and a 1 selects output of the transmit slip buffer. control bits rafrsel0(2-0)-rafrsel31(2-0) (bits 7-5) in registers 040h through 05fh selects the framer from which each time slot is sourced and control bits ratssel0(4-0)-ratssel31(4-0) (bits 4-0) in the same registers selects the time slot within the framer that sources the receive auxiliary port time slot. control bits tdir31 through tdir0 in registers 03ch through 03fh select which side of the framer each time slot from the trans- mit auxiliary port is substituted; a 0 selects the receive slip buffer input and a 1 selects the coder input. con- trol bits tafrsel0(2-0)-tafrsel31(2-0) (bits 7-5) in registers 060h through 07fh selects the framer to which each time slot is supplied and control bits tatssel0(4-0)-tatssel31(4-0) (bits 4-0) in the same regis- ters selects the time slot within the framer that is replaced by the transmit auxiliary port time slot. figure 64. auxiliary port connections decoder coder rx slip buffer tx slip buffer rx slip buffer rx aux i/f tx aux i/f framer channel 1 framer channel 8 radat raclk rasync tadat taclk tasync rx selection logic data tx selection logic data buffer storage & state machine buffer storage & state machine - 147 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. the test access port block, which imple- ments the boundary scan functions, consists of a test access port (tap) controller, instruction and data regis- ters, and a boundary scan register path bordering the input and output leads, as illustrated in figure 65. the boundary scan test bus interface consists of four input signals (i.e., the test clock (tbck), test mode select (tbms), test data input (tbdi) and test reset (trs ) signals) and a test data output (tbdo) output signal. the tap controller receives external control information via a test clock (tbck) signal, a test mode select (tbms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. the instruction and data registers are connected in parallel between the serial test data input (tbdi) and test data output (tbdo) signals. the test data input (tbdi) signal is routed to both the instruction and data regis- ters and is used to transfer serial data into a register during a scan operation. the test data output (tbdo) is selected to send data from either register during a scan operation. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals at the device leads to pass to and from the e1fx8 device?s internal logic, as illustrated in figure 65. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 28. boundary scan support the maximum frequency the e1fx8 device will support for boundary scan is 10 mhz. the e1fx8 device per- forms the following boundary scan test instructions: -extest - sample/preload - idcode -bypass extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruction is shifted in, the e1fx8 device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external e1fx8 input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the e1fx8 device remains fully operational. while in this test mode, e1fx8 input data, and data destined for device outputs, can be captured and shifted out for inspection. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the e1fx8 device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tbdi input, through an internal scan cell, to the tbdo lead. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. idcode test instruction: the format of the idcode test instruction is "10". - 148 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the e1fx8. if boundary scan testing is to be performed and the lead is held low, then a pulldown resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ?input, output and input/output parameters? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. figure 65. boundary scan schematic tap controller data registers instruction register tbdi tbdo in out boundary scan serial test data core logic of e1fx8 boundary scan register signal input and output leads device trs tbck tbms control leads (solder balls on bottom surface of pbga package) - 149 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan chain there are 297 scan cells in the e1fx8 boundary scan chain. the chain is the same in the 256-lead and 208- lead versions except that access to selected leads in the 208-lead version is not available. bidirectional device leads require two scan cells. additional scan cells are used for direction control as needed. the following table shows the listed order of the scan cells and their functions. cells that are not associated with a lead are marked "na"; i/o marked ?internal? are scan cells for internal leads not brought to balls. bsdl files are made available via the product software page of the transwitch internet world wide web site at www.transwitch.com as they are released. scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments 296 internal na na 295 input b4 c5 rclk1 294 input a4 a4 rpos1 293 input c4 b5 rneg1 292 internal na na 291 output3 b5 c6 tneg1 290 output3 a5 d7 tpos1 289 output3 c5 a5 tclk1 288 output3 d5 b6 lcs1 287 internal na na 286 output3 b6 c7 rtclk1 285 input b6 c7 rtclk1 284 output3 a6 a6 rtfrm1 283 input a6 a6 rtfrm1 282 output3 d6 b7 rtsig1 281 output3 d6 a7 rtaux1 280 input b7 c8 e208 279 input a7 b8 conf0 278 control na na tft1cg_enb1 a 0 makes lead ttsig1 an output 277 input c7 a8 conf1 276 output3 d7 d9 rtdat1 275 input b8 c9 ttaix1 274 input a8 b9 ttdat1 273 output3 c8 a9 ttaux1 272 control na na rxc1 a 0 makes leads rtfrm1 and rtclk1 outputs 271 output3 c8 d10 ttsig1 270 input c8 d10 ttsig1 269 input d9 c10 ttfrm1 - 150 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 268 input c9 b10 ttclk1 267 control na na tft1cg_enb2 a 0 makes lead ttsig2 an output 266 input b9 a10 moto 265 output3 a9 a11 rtclk2 264 input a9 a11 rtclk2 263 output3 d10 c11 rtfrm2 262 input d10 c11 rtfrm2 261 output3 c10 b11 rtsig2 260 output3 c10 a12 rtaux2 259 output3 a10 b12 rtdat2 258 input b10 c12 ttaix2 257 control na na rxc2 a 0 makes leads rtfrm2 and rtclk2 outputs 256 input d11 d12 ttdat2 255 output3 c11 a13 ttaux2 254 output3 c11 b13 ttsig2 253 input c11 b13 ttsig2 252 input a11 c13 ttfrm2 251 input b11 a14 ttclk2 250 control na na tfticg_enb3 a 0 makes lead ttsig3 an output 249 output3 d12 b14 rtclk3 248 input d12 b14 rtclk3 247 output3 c12 c14 rtfrm3 246 input c12 c14 rtfrm3 245 output3 a12 a15 rtsig3 244 output3 a12 b15 rtaux3 243 output3 d13 d14 rtdat3 242 input a13 c15 ttaix3 241 input c13 a16 ttdat3 240 control na na rxc3 a 0 makes leads rtfrm3 and rtclk3 outputs 239 output3 b13 b16 ttaux3 238 output3 b13 c16 ttsig3 237 input b13 c16 ttsig3 236 input a14 a17 ttfrm3 235 input b14 a18 ttclk3 scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 151 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 234 output3 a15 d16 rtclk4 233 input a15 d16 rtclk4 232 control na na txaux_en a 0 makes leads taclk and tasync outputs 231 output3 na c17 taclk 230 input na c17 taclk input with pull-up 229 output3 c14 b17 rtfrm4 228 input c14 b17 rtfrm4 227 control na na rxaux_en a 0 makes leads raclk and rasync outputs 226 output3 na a19 raclk 225 input na a19 raclk input with pull-up 224 output3 na a20 rasync 223 input na a20 rasync input with pull-up 222 output3 na c18 tasync 221 input na c18 tasync input with pull-up 220 control na na dpllref_en a 0 makes lead dpllref an output 219 output3 a16 b20 dpllref 218 input a16 b20 dpllref 217 output3 b16 c19 rtsig4 216 input na d18 tadat input with pull-up 215 output3 b16 e17 rtaux4 214 output3 c16 c20 rtdat4 213 input d16 d19 ttaix4 212 control na na rxc4 a 0 makes leads rtfrm4 and rtclk4 outputs 211 input d15 e18 ttdat4 210 output3 d14 d20 ttaux4 209 control na na tfticg_enb4 a 0 makes lead ttsig4 an output 208 output3 d14 e19 ttsig4 207 input d14 e19 ttsig4 206 input e15 f18 ttfrm4 205 input e16 g17 ttclk4 204 output3 e13 e20 monfrm 203 output3 e13 f19 lsdi 202 input e13 f19 lsdi scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 152 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 201 control na na monfrm_en a 0 enables lead lsdi to be an output 200 output3 f15 g18 scout2 199 control na na en_ref_clk2 a 0 enables lead scout2 to be an output 198 input f16 f20 highz 197 internal na na 196 input f14 g19 bposc 195 output3 na g20 radat 194 output3 f13 h18 monclk 193 output3 f13 h19 lsclk 192 output3 g15 h20 mondat 191 control na na mon_en a 0 enables leads mondat, monfrm and monclk to be outputs 190 output3 g15 j17 lsdo 189 control na na spmon_en a 0 enables leads lsdo and lsclk to be outputs 188 output3 g16 j18 d7 187 input g16 j18 d7 186 output3 g13 j19 d6 185 input g13 j19 d6 184 output3 h15 j20 d5 183 input h15 j20 d5 182 output3 h16 k17 d4 181 input h16 k17 d4 180 control na na dt_en a 0 makes leads d0 through d7 outputs 179 output3 h13 k18 d3 178 input h13 k18 d3 177 output3 j13 k19 d2 176 input j13 k19 d2 175 input j14 l20 wr 174 output3 j15 l18 d1 173 input j15 l18 d1 172 output3 k13 l19 d0 171 input k13 l19 d0 170 input k14 m20 rd scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 153 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 169 input k16 m19 sel 168 output3 k15 m18 rdy/dtack 167 internal na na 166 control na na rdy_en a 0 enables lead rdy/dtack to be an output 165 internal na na internal input with pull-down 164 output3 l13 m17 int/irq 163 input l14 n20 reset 162 internal na na 161 input l16 n19 a0 160 input l15 n18 a1 159 input m13 p19 a2 158 input m14 p18 a3 157 input m16 r20 a4 156 input m15 r19 a5 155 input n16 p17 a6 154 input n14 r18 a7 153 input n15 t19 a8 152 input p16 t18 a9 151 input p15 u20 a10 150 input r16 v20 a11 149 internal na na internal input with pull-down 148 internal na na internal input with pull-down 147 internal na na internal input with pull-down 146 input p14 u19 a12 145 internal na na internal input with pull-down 144 internal na na internal input with pull-down 143 internal na na internal input with pull-down 142 output3 r15 v18 scout1 141 control na na en_ref_clk1 a 0 enables lead scout1 to be an output 140 control na na s1ext_b a 0 enables lead sregt to be an output 139 output3 t16 w18 sregt 138 input t16 w18 sregt 137 output3 t15 v17 rtclk5 scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 154 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 136 input t15 v17 rtclk5 135 output3 r14 u16 rtfrm5 134 input r14 u16 rtfrm5 133 output3 t14 y18 rtsig5 132 control na na rxc5 a 0 makes leads rtfrm5 and rtclk5 outputs 131 output3 t14 w17 rtaux5 130 output3 t13 v16 rtdat5 129 input r13 y17 ttaix5 128 input r12 w16 ttdat5 127 output3 t12 v15 ttaux5 126 output3 t12 u14 ttsig5 125 input t12 u14 ttsig5 124 control na na tft1cg_enb5 a 0 makes lead ttsig5 an output 123 input p12 y16 ttfrm5 122 input n12 w15 ttclk5 121 output3 r11 v14 rtclk6 120 input r11 v14 rtclk6 119 output3 t11 y15 rtfrm6 118 input t11 y15 rtfrm6 117 control na na rxc6 a 0 makes leads rtfrm6 and rtclk6 outputs 116 output3 p11 w14 rtsig6 115 output3 p11 y14 rtaux6 114 output3 n11 v13 rtdat6 113 input r10 w13 ttaix6 112 input t10 y13 ttdat6 111 output3 r9 u12 ttaux6 110 input p10 v12 test 109 output3 r9 w12 ttsig6 108 input r9 w12 ttsig6 107 input t9 y12 ttfrm6 106 control na na tft1cg_enb6 a 0 makes lead ttsig6 an output 105 input p9 u11 ttclk6 104 output3 n8 v11 rtclk7 103 input n8 v11 rtclk7 scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 155 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 102 output3 p8 w11 rtfrm7 101 input p8 w11 rtfrm7 100 control na na rxc7 a 0 makes leads rtfrm7 and rtclk7 outputs 99 output3 t8 y11 rtsig7 98 output3 t8 y10 rtaux7 97 output3 r8 v10 rtdat7 96 input n7 w10 ttaix7 95 control na na tft1cg_enb7 a 0 makes lead ttsig7 an output 94 input p7 y9 ttdat7 93output3t7w9ttaux7 92 output3 t7 v9 ttsig7 91 input t7 v9 ttsig7 90 input r7 u9 ttfrm7 89 input n6 y8 ttclk7 88 output3 p6 w8 rtclk8 87 input p6 w8 rtclk8 86 output3 t6 v8 rtfrm8 85 input t6 v8 rtfrm8 84 control na na rxc8 a 0 makes leads rtfrm8 and rtclk8 outputs 83 output3 r6 y7 rtsig8 82 output3 r6 w7 rtaux8 81 output3 n5 v7 rtdat8 80 input p5 y6 ttaix8 79 input r5 w6 ttdat8 78 output3 n4 u7 ttaux8 77 control na na tft1cg_enb8 a 0 makes lead ttsig8 an output 76 output3 n4 v6 ttsig8 75 input n4 v6 ttsig8 74 input t4 y5 ttfrm8 73 input p4 w5 ttclk8 72 input r4 v5 rclk8 71 input t3 y4 rpos8 70 input r3 y3 rneg8 69 input t2 u5 sysci scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 156 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 68 internal na na 67 output3 p3 w4 tneg8 66 internal na na 65 internal na na 64 output3 r2 v2 tpos8 62 output3 t1 t4 tclk8 61 output3 r1 v1 lcs8 60 internal na na 59 input p2 t3 rclk7 58 input p1 u1 rpos7 57 input n1 t2 rneg7 56 output3 n3 r3 tneg7 55 output3 m2 p4 tpos7 54 output3 m1 t1 tclk7 53 output3 m3 r2 lcs7 52 internal na na 51 input m4 r1 rclk6 50 input l2 p2 rpos6 49 input l1 p1 rneg6 48 internal na na 47 output3 l3 n3 tneg6 46 output3 l4 n2 tpos6 45 output3 k2 n1 tclk6 44 internal na na 43 output3 k1 m4 lcs6 42 internal na na 41 input k3 m3 rclk5 40 input k4 m2 rpos5 39 input j2 m1 rneg5 38 internal na na 37 output3 j1 l4 tneg5 36 output3 j3 l3 tpos5 35 output3 j4 l2 tclk5 34 internal na na 33 output3 h4 k1 lcs5 scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 157 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 32 internal na na 31 input h3 k3 rclk4 30 input h1 k2 rpos4 29 input h2 j1 rneg4 28 internal na na 27 output3 g4 j2 tneg4 26 output3 g3 j3 tpos4 25 output3 g1 j4 tclk4 24 internal na na 23 output3 g2 h1 lcs4 22 internal na na 21 input f4 h2 rclk3 20 input f3 h3 rpos3 19 input f1 g1 pwdn 18 input f2 g2 rneg3 17 output3 e4 g3 tneg3 16 output3 e3 f1 tpos3 15 output3 e1 f2 tclk3 14 internal na na 13 internal na na 12 output3 d4 g4 lcs3 11 internal na na 10 input d1 f3 rclk2 9 input d3 e1 rpos2 8 input d2 e2 rneg2 7 output3 c2 e3 tneg2 6 output3 c1 d1 tpos2 5 internal na na 4 output3 b1 c1 tclk2 3 internal na na 2 output3 c3 d2 lcs2 1 internal na na 0 control na na iotri_b a 1 enables the outputs of i/o type output3 scan cell no. i/o lead no. 208 pkg. lead no. 256 pkg. lead symbol comments - 158 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers reset procedure after power-up the e1fx8 requires a hardware reset. this reset will reset all the per channel control registers in the memory map. it will also reset all of the global registers at addresses 004h through 0ffh. a low placed on the reset lead for at least 10 cycles of sysci after all clocks become stable will accomplish the hardware reset. after applying a hardware reset, the entire set of control registers must be programmed to the desired configuration. a global software reset is also available and should be applied at least 40 ms after power-up. this resets the internal state machines; it does not change the state of any of the control registers, performance counters or shadow registers. writing a 1 to control bit reset (bit 7) in register 00ah places the e1fx8 in a reset state. writing a 0 to control bit reset will take the e1fx8 out of the reset state. the reset bit can be read to deter- mine the reset state of the e1fx8. a value of 80h in register 00ah indicates the e1fx8 is in a reset state; a value of 00h indicates the e1fx8 is not in reset. a per channel version of this function is available by writing a 1 to control bit srst (bit 7) in register x+0ah followed by writing a 0 to control bit srst. note that all the mem- ory locations at addresses x+40h through x+1ffh are located in a per channel internal ram and are not reset by either a hardware reset or a software reset. changing the mode of operation of a framer, which includes initializing the framer for the first time after power- up, should be followed by a per channel software reset (srst). the mode bits can be found in framer per channel registers x+00h through x+0ah. not resetting the framer after changing most mode control bits will have minimal effect. however, if control bits bfaa, crca, oof1, oof0, aags (bits 5 and 3-0 in register x+01h), crcmd1, crcmd0 (bits 3 and 2 in register x+07h) and aiw (bit 0 in register x+0ah) are changed, a per channel reset procedure is required. if not all 8 channels of the e1fx8 are implemented in an application, the channels that are not used should be powered down (control bit pwrd, bit 7 in register x+05h is set to a 1) and all interrupts masked (registers x+14h and x+166h are set to ffh). - 159 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers memory map the e1fx8 memory map contains registers and counters which may be accessed by the microprocessor. addresses which are shown as spare, or which are not listed in the memory map, must not be accessed by the microprocessor. the status designation r indicates a read-only unlatched register location, r(l) a read-only latched register location, w a write-only register location and r/w a read/write register location. r and r(l) register bit positions designated as reserved (r) will read out an indeterminate value unless a 0 or 1 read value is indicated. some rw reserved (r) bit positions do not exist (i.e., they have no memory associated with them), so that any values written to these bits cannot be read. those that do have associated memory should be written to 0, as indicated in the following tables. rw reserved (r) bit positions should not be used for stor- age of any application information. common registers device id registers (see descriptions on page 179) customer notebook registers (see descriptions on page 179) global software reset register (see descriptions on page 179) global configuration registers (see descriptions on page 180) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000r11010111 001r01010000 002r11000010 003r00010000 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004 to 009 rw user defined register (e.g., scratch pad) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00a r/w reset reserved, set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00b r/w rise fall gim ipol srgen hwmen dintf r = 0 - 160 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers global status, mask and pointer registers (see descriptions on page 181) line interface control registers (see descriptions on page 186) 00c r/w s1cien synlf enaisi reserved, set to 0 00d r/w spare 00e r/w spare 00f r/w spare 010 r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 011 r glos gais goof grai gcfa goomf gslip gschg 012 r/w gmlos gmais gmoof gmrai gmcfa gmoomf gmslip gmschg 013 r/w spare 014 r chl8 chl7 chl6 chl5 chl4 chl3 chl2 chl1 015 r/w spare 016 r chd8 chd7 chd6 chd5 chd4 chd3 chd2 chd1 017 r gds0rs gds0dc gds0tp gds0tc gintact gintdct goverf gunderf 018 r/w gmds0rs gmds0dc gmds0tp gmds0tc gmintact gmintdct gmoverf gmunderf 019 r chr8 chr7 chr6 chr5 chr4 chr3 chr2 chr1 01a r r gais16 gcrce grai16 r goom16 r = 0 gauxp 01b r/w r=0 gmais16 gmcrce gmrai16 r=0 gmoom16 r = 0 gmauxp 01c r chs8 chs7 chs6 chs5 chs4 chs3 chs2 chs1 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01d r/w bdcst esp espbmon reserved, set to 0 e1chs2 e1chs1 e1chs0 01e r/w lcb7 - lcb0 (command byte) 01f r/w ldo7 - ldo0 (data output to liu) 020 r ldi7 - ldi0 (data input to liu) 021 r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 161 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers monitor control register (see descriptions on page 187) synchronization control registers (see descriptions on page 188) loss of signal detection interval, ones density and code for rai, and ais (trunk condition) registers (see descriptions on page 190) receive and transmit framing pulse (sync) delay control registers (see descriptions on page 191) auxiliary port clock selection and time slot direction registers (see descriptions on page 191) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 022 r/w monrx monrf montr reserved, set to 0 mfr2 mfr1 mfr0 023 r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 024 r/w s18khz s1ctri s1yncen s1sextb s1sint s1ync2 s1ync1 s1ync0 025 r/w s28khz s2ctri s2yncen reserved, set to 0 s2ync2 s2ync1 s2ync0 026-029 r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02a r/w losi7 -losi0 02b r/w enlosi r = 0 ond5 -ond0 02c r/w coderai(3-0) codeais(3-0) 02d r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02e r/w rfrm7-rfrm0 (frame pulse delay, rfrm7 = bit 7) 02f r/w tfrm7-tfrm0 (frame pulse delay, tfrm7 = bit 7) 030 r spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 037 r/w reserved, set to 0 concaten tacksel tadirsel racksel radirsel - 162 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers auxiliary port receive and transmit data selection registers (see descriptions on page 192) 038 r/w rdir7 rdir6 rdir5 rdir4 rdir3 rdir2 rdir1 rdir0 039 r/w rdir15 rdir14 rdir13 rdir12 rdir11 rdir10 rdir9 rdir8 03a r/w rdir23 rdir22 rdir21 rdir20 rdir19 rdir18 rdir17 rdir16 03b r/w rdir31 rdir30 rdir29 rdir28 rdir27 rdir26 rdir25 rdir24 03c r/w tdir7 tdir6 tdir5 tdir4 tdir3 tdir2 tdir1 tdir0 03d r/w tdir15 tdir14 tdir13 tdir12 tdir11 tdir10 tdir9 tdir8 03e r/w tdir23 tdir22 tdir21 tdir20 tdir19 tdir18 tdir17 tdir16 03f r/w tdir31 tdir30 tdir29 tdir28 tdir27 tdir26 tdir25 tdir24 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 040 r/w rafrsel0(2-0) ratssel0(4-0) 041 r/w rafrsel1(2-0) ratssel1(4-0) 042 r/w rafrsel2(2-0) ratssel2(4-0) 043 r/w rafrsel3(2-0) ratssel3(4-0) 044 r/w rafrsel4(2-0) ratssel4(4-0) 045 r/w rafrsel5(2-0) ratssel5(4-0) 046 r/w rafrsel6(2-0) ratssel6(4-0) 047 r/w rafrsel7(2-0) ratssel7(4-0) 048 r/w rafrsel8(2-0) ratssel8(4-0) 049 r/w rafrsel9(2-0) ratssel9(4-0) 04a r/w rafrsel10(2-0) ratssel10(4-0) 04b r/w rafrsel11(2-0) ratssel11(4-0) 04c r/w rafrsel12(2-0) ratssel12(4-0) 04d r/w rafrsel13(2-0) ratssel13(4-0) 04e r/w rafrsel14(2-0) ratssel14(4-0) 04f r/w rafrsel15(2-0) ratssel15(4-0) 050 r/w rafrsel16(2-0) ratssel16(4-0) 051 r/w rafrsel17(2-0) ratssel17(4-0) 052 r/w rafrsel18(2-0) ratssel18(4-0) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 163 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 053 r/w rafrsel19(2-0) ratssel19(4-0) 054 r/w rafrsel20(2-0) ratssel20(4-0) 055 r/w rafrsel21(2-0) ratssel21(4-0) 056 r/w rafrsel22(2-0) ratssel22(4-0) 057 r/w rafrsel23(2-0) ratssel23(4-0) 058 r/w rafrsel24(2-0) ratssel24(4-0) 059 r/w rafrsel25(2-0) ratssel25(4-0) 05a r/w rafrsel26(2-0) ratssel26(4-0) 05b r/w rafrsel27(2-0) ratssel27(4-0) 05c r/w rafrsel28(2-0) ratssel28(4-0) 05d r/w rafrsel29(2-0) ratssel29(4-0) 05e r/w rafrsel30(2-0) ratssel30(4-0) 05f r/w rafrsel31(2-0) ratssel31(4-0) 060 r/w tafrsel0(2-0) tatssel0(4-0) 061 r/w tafrsel1(2-0) tatssel1(4-0) 062 r/w tafrsel2(2-0) tatssel2(4-0) 063 r/w tafrsel3(2-0) tatssel3(4-0) 064 r/w tafrsel4(2-0) tatssel4(4-0) 065 r/w tafrsel5(2-0) tatssel5(4-0) 066 r/w tafrsel6(2-0) tatssel6(4-0) 067 r/w tafrsel7(2-0) tatssel7(4-0) 068 r/w tafrsel8(2-0) tatssel8(4-0) 069 r/w tafrsel9(2-0) tatssel9(4-0) 06a r/w tafrsel10(2-0) tatssel10(4-0) 06b r/w tafrsel11(2-0) tatssel11(4-0) 06c r/w tafrsel12(2-0) tatssel12(4-0) 06d r/w tafrsel13(2-0) tatssel13(4-0) 06e r/w tafrsel14(2-0) tatssel14(4-0) 06f r/w tafrsel15(2-0) tatssel15(4-0) 070 r/w tafrsel16(2-0) tatssel16(4-0) 071 r/w tafrsel17(2-0) tatssel17(4-0) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 164 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers spare register locations other control registers (see descriptions on page 193) 072 r/w tafrsel18(2-0) tatssel18(4-0) 073 r/w tafrsel19(2-0) tatssel19(4-0) 074 r/w tafrsel20(2-0) tatssel20(4-0) 075 r/w tafrsel21(2-0) tatssel21(4-0) 076 r/w tafrsel22(2-0) tatssel22(4-0) 077 r/w tafrsel23(2-0) tatssel23(4-0) 078 r/w tafrsel24(2-0) tatssel24(4-0) 079 r/w tafrsel25(2-0) tatssel25(4-0) 07a r/w tafrsel26(2-0) tatssel26(4-0) 07b r/w tafrsel27(2-0) tatssel27(4-0) 07c r/w tafrsel28(2-0) tatssel28(4-0) 07d r/w tafrsel29(2-0) tatssel29(4-0) 07e r/w tafrsel30(2-0) tatssel30(4-0) 07f r/w tafrsel31(2-0) tatssel31(4-0) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 031 - 036 080 - 0fd r/w reserved, set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0fe r/w reserved, set to 0 resecksyn disecksyn debval(3-0) 0ff r/w wg reserved, set to 0 obt1si reserved, set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 165 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers per channel control and status indication registers the following registers configure, control or provide status information on a per channel (framer) basis. the memory map uses a 13-bit address, with the 9 least significant bits addressing 512 per framer or common (glo- bal) registers and the 4 most significant bits used to address a framer (from 1 to 8) or the common registers. the first 512 addresses are used for the common registers described above. each framer?s register range (x+00h to x+ffh) is 512 addresses, as shown below: framer configuration and control registers (see descriptions on page 195) receiver fractional e1 channel control registers (see descriptions on page 205) framer channel address range (hex) x = (hex) common 0000 - 01ff 0000 framer no. 1 0200 - 03ff 0200 framer no. 2 0400 - 05ff 0400 framer no. 3 0600 - 07ff 0600 framer no. 4 0800 - 09ff 0800 framer no. 5 0a00 - 0bff 0a00 framer no. 6 0c00 - 0dff 0c00 framer no. 7 0e00 - 0fff 0e00 framer no. 8 1000 - 11ff 1000 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+00 r/w rail be rxcp rxnrz exlos elosn enzc ts16eic x+01 r/w rtfm ttfm bfaa casa crca oof1 oof0 aags x+02 r/w enais enoof enlos enabit endbit rtais enrai rtrai x+03 r/w rx0aise rt0ais rx0rai rt0rai enrxnbr eoocrc eoo16m enrxauxp x+04 r/w rdinv rsinv tdinv tsinv rdadi tdadi enraia enraiy x+05 r/w pwrd fdat fpol syfz txcp txnrz enlais e16ais x+06 r/w txais txrai extais extrai entxauxp ulaw tx0aise st0ais x+07 r/w tdfme txdrv tlmf fe1m crcmd1 crcmd0 tais16e ts16ye x+08 r/w bpcrc4 sa4up sa5up sa6up sa7up sa8up autrai auty x+09 r/w reserved, set to 0 x+0a r/w srst rsync reserved, set to 0 aiw address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+1a r/w rchmk reserved, set to 0 - 166 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit fractional e1 channel, digital milliwatt and idle code control registers (see descriptions on page 205) receive and transmit facility data link control registers (see descriptions on page 207) x+1b r/w rfch7-rfch0 (receive fractional e1 channels 7-0) x+1c r/w rfch15-rfch8 (receive fractional e1 channels 15-8) x+1d r/w rfch23-rfch16 (receive fractional e1 channels 23-16) x+1e r/w rfch31-rfcg24 (receive fractional e1 channels 31-24) x+1f r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+110 r/w tchmk reserved, set to 0 x+111 r/w tc1c3 tc0c3 tc1c2 tc0c2 tc1c1 tc0c1 tc1c0 tc0c0 x+112 r/w tc1c7 tc0c7 tc1c6 tc0c6 tc1c5 tc0c5 tc1c4 tc0c4 x+113 r/w tc1c11 tc0c11 tc1c10 tc0c10 tc1c9 tc0c9 tc1c8 tc0c8 x+114 r/w tc1c15 tc0c15 tc1c14 tc0c14 tc1c13 tc0c13 tc1c12 tc0c12 x+115 r/w tc1c19 tc0c19 tc1c18 tc0c8 tc1c17 tc0c17 tc1c16 tc0c16 x+116 r/w tc1c23 tc0c23 tc1c22 tc0c22 tc1c21 tc0c21 tc1c20 tc0c20 x+117 r/w tc1c27 tc0c27 tc1c26 tc0c26 tc1c25 tc0c25 tc1c24 tc0c24 x+118 r/w tc1c31 tc0c31 tc1c30 tc0c30 tc1c29 tc0c29 tc1c28 tc0c28 x+119 r/w idl7-idl0 (idle code written by microprocessor), where idl7 is bit 1 transmitted x+161 r/w reserved set to 0 attnlim recenter bypass address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+122 r/w reserved, set to 0 bnal reserved, set to 0 x+123 r/w ehr rhie reserved, set to 0 x+124 r rhd7 - rhd0 (hdlc receive data, rhd0 is the first bit received on the line) x+125 r dpt7 - dpt0 (hdlc receive fifo depth) x+126 r/w eht tab eom r=0 thie reserved, set to 0 x+127 w thd7 - thd0 (hdlc transmit data, thd0 is the first bit transmitted on the line) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 167 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit facility data link status registers (see descriptions on page 209) receive and transmit slip buffer control registers (see descriptions on page 211) receive and transmit slip buffer status registers (see descriptions on page 212) receive and transmit slip buffer pointer status registers (see descriptions on page 213) x+128 r r msl6 msl5 msl4 msl3 msl2 msl1 msl0 x+0c r/w reserved set to 0 sa4 sa5 sa6 sa7 sa8 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+0d r/w lrhis2 lrhis1 lrhis0 lrxfs1 lrxfs0 ltxfs1 ltxfs0 lthis x+0e r rhis2 rhis1 rhis0 rxfs1 rfxs0 txfs1 txfs0 this x+0f r/w mrhis2 mrhis1 mrhis0 mrxfs1 mrxfs0 mtxfs1 mtxfs0 mthis x+160 r/w reserved, set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+11b r/w rxcke r = 0 rxsbe rsr reserved; set to 0 x+11c r/w txc1 txc0 txsbe tsr reserved; set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+15 r rxs1 rxs0 rtslpp reserved x+16 r txs1 txs0 ltslpp reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+20 r/w rwp7-trp0 (receive slip buffer write pointer) x+21 r/w rrp7-rrp0 (receive slip buffer read pointer) x+22 r/w rwsbs reserved rwpf3-rwpf0 (receive write pointer frame) x+23 r/w rrsbs rxsbd8 reserved rrpf3-rrpf0 (receive read pointer frame) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 168 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive slip buffer control registers (see descriptions on page 215) receive slip buffer frame storage registers (see descriptions on page 217) x+24 r rxsbd7-rxsbd0 (receive slip buffer delay in increments of 1 bits) x+25 r txsbd7-txsbd0 (transmit slip buffer delay in increments of 1 bits) x+26 r/w twp7-twp0 (transmit slip buffer write pointer) x+27 r/w trp7-trp0 (transmit slip buffer read pointer x+28 r/w twsbs reserved twpf3-twpf0 (transmit write pointer frame) x+29 r/w trsbs txsbd8 reserved trpf3-trpf0 (transmit read pointer frame) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+3a r/w reserved, set to 0 rx2s rx1s rx0s x+3b r/w rsis reserved, set to 0 rsa4s rsa5s rsa6s rsa7s rsa8s x+3c r/w rde7-rde1 (receive time slots 7-1 selection) r=0 x+3d r/w rde15-rde8 (receive time slots 15-8 selection) x+3e r/w rde23-rde16 (receive time slots 23-16 selection) x+3f r/w rde31-rde24 (receive time slots 31-24 selection) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+40 r/w rfas - receive frame alignment pattern fas channel 1 (time slot 0 - frame 1) x+41 to x+5f r/w frame 1 rts1-rts31 (receive time slots ts1 - ts31) x41 - time slot 1 x5f - time slot 31 x+60 r/w rnfas - receive no frame alignment pattern nfas channel 1 (time slot 0 - frame 1) x+61 to x+7f r/w frame 2 rts1-rts31 (receive time slots ts1 - ts31) x61 - time slot 1 x7f - time slot 31 x+132 r/w reserved, set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 169 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit slip buffer control registers (see descriptions on page 218) transmit slip buffer frame storage registers (see descriptions on page 220) receive and transmit signaling state control registers (see descriptions on page 221) receive signaling control registers (see descriptions on page 222) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+e2 r/w reserved, set to 0 tx2s tx1s tx0s x+e3 r/w tsis reserved, set to 0 tsa4s tsa5s tsa6s tsa7s tsa8s x+e4 r/w tde7-tde1 (transmit time slots 7-1 selection) r=0 x+e5 r/w tde15-tde8 (transmit time slots 15-8 selection) x+e6 r/w tde23-tde16 (transmit time slots 23-16 selection) x+e7 r/w tde31-tde24 (transmit time slots 31-24 selection) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+90 r/w tfas - transmit frame alignment pattern fas channel 1 (time slot 0 - frame 1) x+91 to x+af r/w frame 1 tts1-tts31 (transmit time slots ts1 - ts31) x91 - time slot 1 xaf - time slot 31 x+b0 tnfas - transmit no frame alignment pattern nfas channel 1 (time slot 0 - frame 1) x+b1 to x+cf r/w frame 2 tts1-tts31 (transmit time slots ts1 - ts31) xb1 - time slot 1 xcf - time slot 31 x+133 r/w reserved; set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+134 r/w typ1 typ0 ts0fz sigdb sigien r = 0 rxsfz txsfz address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+e8 r/w rse8-rse1 (receive signaling enable for channels 8-1 selection) x+e9 r/w rse16-rse9 (receive signaling enable for channels 16-9 selection) - 170 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling state registers (debounce buffer) (see descriptions on page 223) receive signaling state registers (active buffer 1) (see descriptions on page 227) receive signaling state match count registers (see descriptions on page 232) x+ea r/w rse24-rse17 (receive signaling enable for channels 24-17 selection) x+eb r/w reserved, set to 0 rse30-rse25 (receive signaling enable for channels 30-25 selection) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+80 r/w receive multiframe pattern rsigmas (0000) rx0 ry rx1 rx2 x+81 to x+8f r/w receive signaling bits ra1-rd1 (a1 b1 c1 d1) to ra15-rd15 (a15 b15 c15 d15) receive signaling bits ra16-rd16 (a16 b16 c16 d16) to ra30-rd30 (a30 b30 c30 d30) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+137 r/w receive multiframe pattern rrsigmas (0000) rrx0 rry rrx1 rrx2 x+138 to x+146 r/w receive signaling bits rra1-rrd1 (a1 b1 c1 d1) to rra15-rrd15 (a15 b15 c15 d15) receive signaling bits rra16-rrd16 (a16 b16 c16 d16) to rra30-rrd30 (a30 b30 c30 d30) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+147 r/w reserved x+148 r/w rsnm1(3-0) rsnm16(3-0) x+149 r/w rsnm2(3-0) rsnm17(3-0) x+14a r/w rsnm3(3-0) rsnm18(3-0) x+14b r/w rsnm4(3-0) rsnm19(3-0) x+14c r/w rsnm5(3-0) rsnm20(3-0) x+14d r/w rsnm6(3-0) rsnm21(3-0) x+14e r/w rsnm7(3-0) rsnm22(3-0) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 171 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit signaling control registers (see descriptions on page 239) transmit signaling state registers (see descriptions on page 241) e1 line status registers (see descriptions on page 245) x+14f r/w rsnm8(3-0) rsnm23(3-0) x+150 r/w rsnm9(3-0) rsnm24(3-0) x+151 r/w rsnm10(3-0) rsnm25(3-0) x+152 r/w rsnm11(3-0) rsnm26(3-0) x+153 r/w rsnm12(3-0) rsnm27(3-0) x+154 r/w rsnm13(3-0) rsnm28(3-0) x+155 r/w rsnm14(3-0) rsnm29(3-0) x+156 r/w rsnm15(3-0) rsnm30(3-0) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+ec r/w tse8-tse1 (transmit signaling enable for channels 8-1 selection) x+ed r/w tse16-tse9 (transmit signaling enable for channels 16-9 selection) x+ee r/w tse24-tse17 (transmit signaling enable for channels 24-17 selection) x+ef r/w reserved, set to 0 tse30-tse25 (transmit signaling enable for channels 30-25 selection) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+d0 r/w transmit multiframe pattern tsigmas (0000) tx0 ty tx1 tx2 x+d1 to x+df r/w transmit signaling bits ta1-td1 (a1 b1 c1 d1) to ta15-td15 (a15 b15 c15 d15) transmit signaling bits ta16-td16 (a16 b16 c16 d16) to ta30-td30 (a30 b30 c30 d30) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+10 r los ais oof rai cfa oofm slip schg x+11 r/w llos lais loof lrai lcfa loofm lslip lschg address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 172 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers non-interrupt status registers (see descriptions on page 254) transmit sa4 - sa8 code registers (see descriptions on page 255) x+12 r/w plos pais poof prai pcfa poofm pslip pschg x+13 r/w flos fais foof frai fcfa foofm fslip fschg x+14 r/w mlos mais moof mrai mcfa moofm mslip mschg x+164 r r=0 ais16 ecrce rai16 r=0 oo16m r=0 auxp x+165 r/w r=0 lais16 lecrce lrai16 r=0 loo16m r=0 lauxp x+166 r/w r=0 mais16 mecrce mrai16 r=0 moo16m r=0 mauxp x+167 r/w r=0 pais16 pecece prai16 r=0 poo16m r=0 pauxp x+168 r/w r=0 fais16 fecrce frai16 r=0 foo16m r=0 fauxp address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+17 r reserved, set to 0 tabit tybit reserved, set to 0 rxsf txsf x+18 r ncrc4 reserved ts16me reserved x+19 r to clear sigact7-sigact0 x+175 r reserved s6x s6f s6e s6c s6a s68 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+169 r/w xsa47-xsa40 x+16a r/w xsa57-xsa50 x+16b r/w xsa67-xsa60 x+16c r/w xsa77-xsa70 x+16d r/w xsa87-xsa80 x+16e r/w spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 173 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive sa4 - sa8 code registers (see descriptions on page 256) performance counters and counters shadow registers (see descriptions on page 257) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+16f r rsa47-rsa40 x+170 r rsa57-rsa50 x+171 r rsa67-rsa60 x+172 r rsa77-rsa70 x+173 r rsa87-rsa80 x+174 r spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+f0 r/w lcrc7-lcrc0 (latched crc-4 error counter shadow register 10 bits) x+f1 r/w lcrco reserved, set to 0 lcrc9 lcrc8 x+f2 r/w crc7-crc0 (crc-4 error counter 10 bits) x+f3 r/w crco reserved, set to 0 crc9 crc8 x+f4 r/w lcv7-lcv0 (latched coding violations error counter shadow register 16 bits) x+f5 r/w lcv15-lcv8 (latched coding violations error counter shadow register 16 bits) x+f6 r/w lcvo reserved, set to 0 x+f7 r/w cv7-cv0 (coding violations error counter 16 bits) x+f8 r/w cv15-cv8 (coding violations error counter 16 bits) x+f9 r/w cvo reserved, set to 0 x+fa r/w lfbe7-lfbe0 (latched framing word error counter shadow register 8 bits) x+fb r/w lfbeo reserved, set to 0 x+fc r/w fbe7-fbe0 (framing word error counter 8 bits) x+fd r/w fbeo reserved, set to 0 x+fe r/w lebe7-lebe0 (latched e-bit error counter shadow registers, 10 bits) x+ff r/w lebeo reserved, set to 0 lebe9 lebe8 x+100 r/w ebe7-lebe0 (e-bit error counter, 10 bits) x+101 r/w ebeo reserved, set to 0 ebe9 ebe8 - 174 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers test generation registers (see descriptions on page 263) time slot/ds0 loopback, test pattern status and dpll status registers (see descriptions on page 265) x+102 to x+105 r/w reserved, set to 0 x+157 r/w ltestp7-ltestp0(latched lower byte test analyzer ool counter) x+158 r/w ltestpo ltestp14-ltestp8(latched upper byte test analyzer ool counter) x+159 r/w testp7-testp0(lower byte test analyzer ool counter) x+15a r/w testpo testp14-testp8(upper byte test analyzer ool counter) x+177 r/w lsa617-lsa610(latched lower byte) x+178 r/w lsa61o reserved, set to 0 lsa619 lsa618 x+179 r/w sa617-sa610(lower byte) x+17a r/w sa61o reserved, set to 0 sa619 sa618 x+17b r/w lsa627-lsa620(latched lower byte) x+17c r/w lsa62o reserved, set to 0 lsa629 lsa628 x+17d r/w sa627-sa620(lower byte) x+17e r/w sa62o reserved, set to 0 sa629 sa628 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+106 r/w crce frme bpve nfase reserved; set to 0 prbre inprbs x+107 r/w llp txlais rlp plp reserved; set to 0 sprbre sinprbs x+108 r/w reserved; set to 0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+129 r ds0act ds0dct tplol ds0txc intact intdct overf underf x+12a r/w lds0act lds0dct ltplol lds0txc lintact lintdct loverf lunderf x+12b r/w mdact mddct mtplol mds0txc mintact mintdct moverf munderf address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 175 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot/ds0 test pattern control registers (see descriptions on page 268) test registers (see descriptions on page 271) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+109 r/w tsrlop ds0da trdslp trpn2 tprn1 tprn0 tsllp rlpen x+10a r/w tsrl8 tsrl7 tsrl6 tsrl5 tsrl4 tsrl3 tsrl2 tsrl1 x+10b r/w tsrl16 tsrl15 tsrl14 tsrl13 tsrl12 tsrl11 tsrl10 tsrl9 x+10c r/w tsrl24 tsrl23 tsrl22 tsrl21 tsrl20 tsrl19 tsrl18 tsrl17 x+10d r/w tsrl32 tsrl31 tsrl30 tsrl29 tsrl28 tsrl27 tsrl26 tsrl25 x+12c r/w srtt7-srtt0 x+12d r/w tsll8 tsll7 tsll6 tsll5 tsll4 tsll3 tsll2 tsll1 x+12e r/w tsll16 tsll15 tsll14 tsll13 tsll12 tsll11 tsll10 tsll9 x+12f r/w tsll24 tsll23 tsll22 tsll21 tsll20 tsll19 tsll18 tsll17 x+130 r/w tsll32 tsll31 tsll30 tsll29 tsll28 tsll27 tsll26 tsll25 x+131 r/w reserved, set to 0 sprn rtpae ssprn srtpae x+15b r/w test word first byte x+15c r/w test word second byte x+15d r/w test word third byte x+15e r/w test word fourth byte address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+17f to x+1fe r/w reserved x+1ff r/w reserved, set to 0 oblol rxfs r = 0 - 176 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers spare and reserved registers spare registers registers that are not assigned to functions, or reserved, are designated as spare. spare registers must not be accessed for read or write operations by the microprocessor. the following registers are spares: 00d through 010, 013, 015, 021, 023, 026 through 029, 02d, 030, 031 through 036, 080 through 0fd, x+0b, x+1f, x+2a, x+2b, x+2c, x+2d, x+2e, x+2f, x+11a, x+135, x+136, x+162, x+16e, x+174. reserved and test registers the following bit locations in read/write registers are designated as reserved, and some require zeros to be written into them as indicated in the tables below. some of these bits are designated as internal test bits, etc. per framer test registers may be read but must not be written during normal operation. global registers per framer registers register bits comments 00a 6-0 set to zero 00b 0 set to zero 00c 4-0 set to zero 01a 1 set to zero 01a 7, 3 01b 7, 3, 1 set to zero 01d 4, 3 set to zero 022 4, 3 set to zero 025 4, 3 set to zero 02b 6 set to zero 037 7-5 set to zero 0ff 1, 0 set to zero register bits comments x+09 7-0 set to zero x+0a 5-1 set to zero x+0c 7-5 set to zero x+15 4-0 x+16 4-0 x+1a 6-0 set to zero x+22 6-4 x+23 5, 4 x+28 6-4 - 177 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+29 5, 4 x+36 7-0 x+37 7-0 x+3a 7-3 set to zero x+3b 6, 5 set to zero x+3c 0 set to zero x+58-x+5f 7-0 x+78-x+7f 7-0 x+e2 7-3 set to zero x+e3 6, 5 set to zero x+e4 0 set to zero x+eb 7-6 x+ef 7-6 x+f1 6-2 set to zero x+f3 6-2 set to zero x+f6 6-0 set to zero x+f9 6-0 set to zero x+fb 6-0 set to zero x+fd 6-0 set to zero x+ff 6-2 set to zero x+101 6-2 set to zero x+102- x+105 7-0 set to zero x+106 3, 2 set to zero x+107 3, 2 set to zero x+108 7-0 set to zero x+110 6-0 set to zero x+11b 6, 3-0 set to zero x+11c 3-0 set to zero x+122 4-0 set to zero x+123 5-0 set to zero x+126 4 set to zero x+131 7-4 set to zero x+132 7-0 set to zero x+133 7-0 set to zero register bits comments - 178 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+134 2 set to zero x+147 7-0 x+160 7-0 set to zero x+163 7-0 set to zero x+165- x+168 7, 3, 1 set to zero x+178 6-2 set to zero x+17a 6-2 set to zero x+17c 6-2 set to zero x+17e 6-2 set to zero x+17f- x+1fe 7-0 x+1ff 7-3, 0 set to zero register bits comments - 179 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers memory map descriptions common registers device id registers the manufacturer id, part number code and version of the e1fx8 are implemented in registers 000h - 003h with read-only capability, as shown in the memory map section. the manufacturer id is 107 (decimal), and has been assigned for transwitch by the joint electron device engineering council (jedec) of the solid state products engineering council. this field is 11 bits in length, and is assigned to bits 3 through 0 in register 001h, and bits 7 through 1 in register 000h. bit 0 in register 000h (lsb) is assigned to the value 1. the 11 bit manufacturer id plus the lsb contains value 0d7h. the part number is 16 bits long. the part number code used here for the e1fx8 is 03109 (decimal). the binary equivalent of 03109 (decimal) is assigned to bits 3-0 in register 003h, bits 7-0 in register 002h, and bits 7-4 (lsb) in register 001h (0c25h). the revision level field at bits 7-4 in register 003h represents the version number of the device and is set to 1h, but this value may be changed as the device evolves. msb lsb customer notebook register global software reset register the control bit in this read/write register location is used for resetting the e1fx8. version part number manufacturer identify 1 4 bits 16 bits 11 bits 1 bit address (hex) bit symbol description 004 to 009 7-0 notebook user defined register: the bits in this read/write register are provided for use by the application software. the contents of this read/write register will have no direct effect on the operation of the e1fx8. address (hex) bit symbol description 00a 7 reset software reset: this register location is provided in addition to the hardware reset for resetting internal state machines. performance counters and shadow registers must be written to 0 if it is desired to clear them; if control bit srgen (register 00bh, bit 3) is set to a 1, a one-second clock from the sregt lead or a selected derived clock will clear these counters and regis- ters. the reset will be released when a 0 is written into this bit position. 6-0 reserved: write these bits to 0. - 180 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers global configuration registers the bits in these read/write registers control e1fx8 operations on a global basis for all eight framers. address (hex) bit symbol description 00b 7 rise rising edge latched status event selection: this control bit works in con- junction with the fall control bit for controlling the edge for latching an alarm. rise fall action 0 0 the latched bit indications for all 8 framers will be disabled. the hardware interrupt is disabled. 0 1 latched status indication bits for all framers set on negative transitions (off state) of an alarm. 1 0 latched status indication bits for all framers set on positive transitions (on state) of an alarm. 1 1 latched status indication bits for all framers set on positive or negative transitions of an alarm. 6fall falling edge latched status event selection: this control bit works in con- junction with the rise control bit (described above) for controlling the edge for latching an alarm, as defined in the table given above. 5gim global interrupt mask disable: a 1 disables (masks) the hardware interrupt lead. when set to 0, the hardware interrupt lead is enabled. 4ipol interrupt polarity sense control: a 1 will invert the polarity of the hardware interrupt from active high to active low for the intel compatible microprocessor bus, and from active low to active high for the motorola compatible micropro- cessor bus. 3srgen shadow register feature enabled: a 1 will enable the shadow register fea- ture; must be set for pm/fm and counter latching. 2hwmen hardware mask hierarchy enable: when this bit is set to 1, the masking hierarchy for the alarms is enabled according to the table below: 1dintf data interface enable: a 1 will configure the system side interface for data operation for the transmission interface. in h-mvip mode a 1 will select a two clock cycle sync. pulse (h.100 timing); a 0 defaults h-mvip to a four clock cycle sync. pulse. 0 reserved: write this bit to 0. alarm suppression table (shaded columns indicate suppressed alarms) direction los line ais oof ts16 ais rai crc oomf ts16 oomf ts16 rai ts16 me line port to system x x x x - 181 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers global status, mask and pointer registers these registers are read-only, except for the mask registers 012h, 018h and 01bh, which are read/write. the bits in the global status indication registers 011h and 01ah indicate an alarm caused by a line time slot 0 or time slot 16 event on a global basis (i.e., in any framer). each global status indication bit is formed by or-gating the corresponding latched event bits in each of the eight framer channels (registers x+11h or x+164h) to pro- vide the individual status indication in global registers 011h and 01ah. a 1 written into a bit position in the global mask register 012h or 01bh will mask the interrupt indication for the corresponding bit position in register 011h or 01ah. the bits in register locations 014h and 01bh provide a pointer to the framer or framers which caused the line latched event. a similar procedure is supported for hdlc events and ds0 loop back activate and deac- tivate codes. for hdlc events a separate pointer is provided by register 016h which indicates which framer or framers caused the latched event; there are no global mask bits for hdlc events since they are provided on a per framer basis. for ds0 loop back activity and the prbs/code word analyzer, the bits in the global status indication register 017h indicate an alarm caused by an analyzer out of lock, an activate/deactivate pattern or a complete activate/deactivate code received on a global basis (i.e., in any framer). each global status indica- tion bit is formed by or-gating the corresponding latched event bits in each of the eight framer channels (registers x+129h) to provide the individual status indication in global register 017h. a 1 written into a bit position in the global mask register 018h will mask the interrupt indication for the corresponding bit position in register 017h. the bits in register locations 019h provide a pointer to the framer or framers which caused the latched event. 00c 7 s1cien substitution clock on los enable: a 1 enables an the external clock to be substituted for the receive line clock when an loss of signal alarm is detected. 6synlf synchronous framing pulse to line frame: a 1 causes the 8 khz framing pulse (when enabled) on the scout1 and scout2 leads to be synchronous with the start of time slot 0 in the receive line signal. the exact phase is a function of the codec option (nrz, ami / hdb3) and clock edge option (rxcp = 1,0) selected. see descriptions for leads scout1 and scout2 in the lead description section, and associated timing diagrams. 5enaisi enable ais detection per isdn: when set to a 1 ais is detected as defined in itu-t i.431; ais is declared if two or less zeros are detected in two consecutive frames (one double frame); ais is cleared when three or more zeros are detected in a double frame after basic frame alignment. when set to a 0, ais is detected per itu-t g.775; ais is declared if two or less zeros are detected in two consecutive double frames (4 frames total); ais is cleared when three or more zeros are detected in a two consecutive doubles frame after basic frame alignment. 4-0 reserved: write these bits to 0. address (hex) bit symbol description 011 7 glos global indication for loss of signal: this bit position indicates when any of the 8 framers has detected a loss of signal. this bit position is cleared when the corresponding framer alarm is cleared. address (hex) bit symbol description - 182 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 011 (cont.) 6gais global indication for ais: this bit position indicates when any of the 8 fram- ers has detected an ais. this bit position is cleared when the corresponding framer alarm is cleared. 5 goof global indication for out of frame: this bit position indicates when any of the 8 framers has detected an out of frame. this bit position is cleared when the corresponding framer alarm is cleared. 4grai global indication for rai (a-bit = 1) indication: this bit position indicates when any of the 8 framers has detected an rai indication. this bit position is cleared when the corresponding framer alarm is cleared. 3gcfa global indication for change in frame alignment: this bit position indicates when any of the 8 framers has detected an change in frame alignment indi- cation. this bit position is cleared when the corresponding framer alarm is cleared. 2 goomf global indication for out of multiframe alignment error: this bit will be set if there is an out of multiframe error in any of the 8 framers. this bit will be cleared when all oomf errors have been cleared in the individual channel event registers. 1gslip global indication for transmit or receive slip alarm: this bit position indi- cates when any of the 8 framers has detected a transmit or receive slip. this bit position is cleared when the corresponding framer alarm is cleared. 0gschg global indication for change of signaling: this bit position indicates when any of the 8 framers has detected a debounced signaling bit change. this bit position is cleared when the corresponding framer alarm is cleared. 012 7 gmlos global loss of signal mask bit: when set to 1, this bit disables the hardware interrupt for a loss of signal indication from any of the 8 framers. 6gmais global ais mask bit: when set to 1, this bit disables the hardware interrupt for an ais indication from any of the 8 framers. 5gmoof global out of frame mask bit: when set to 1, this bit disables the hardware interrupt for an oof indication from any of the 8 framers. 4gmrai global rai (a-bit = 1) indication mask bit: when set to 1, this bit disables the hardware interrupt for an rai indication from any of the 8 framers. 3gmcfa global change in frame alignment mask bit: when set to 1, this bit disables the hardware interrupt for a cfa from any of the 8 framers. 2gmoomf global out of multiframe mask bit: when set to 1, this bit disables the hard- ware interrupt for a oomf from any of the 8 framers. 1gmslip global transmit or receive slip mask bit: when set to 1, this bit disables the hardware interrupt for a transmit or receive slip indication from any of the 8 framers. 0 gmschg global transmit slip mask bit: when set to 1, this bit disables the hardware interrupt for a debounced signaling bit change indication from any of the 8 framers. address (hex) bit symbol description - 183 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 014 7-0 chl8- chl1 channel activity line event for channels 1 through 8: when a bit is set to 1, it indicates the framer (1 through 8) that caused the global line indication (los, ais, oof, rai, cfa, slip, or schg alarms). 016 7-0 chd8- chd1 channel activity hdlc event for channels 1 through 8: when a bit is set to 1, it indicates the framer (1 through 8) that caused the global hdlc indication (receive or transmit). 017 7 gds0rs global indication for ds0 receive remote loopback activate request indication: this bit position indicates when any of the 8 framers has detected a ds0 remote loopback activate request. this bit position is cleared when the corresponding framer indication is cleared. 6gds0dc global indication for ds0 receive remote loopback deactivate request indication: this bit position indicates when any of the 8 framers has detected a ds0 remote loopback deactivate request. this bit position is cleared when the corresponding framer indication is cleared. 5gds0tp global indication for time slot receive out of lock indication: this bit posi- tion indicates when any of the 8 framers has detected a time slot out of lock indication for a time slot test pattern. this bit position is cleared when the corresponding framer indication is cleared. 4gds0tc global indication for ds0 transmit remote loopback sequence complete: this bit position indicates when any of the 8 framers has completed transmit- ting a ds0 remote loopback activate/deactivate request. this bit position is cleared when the corresponding framer indication is cleared. 3gintact global intermediate indication for ds0 receive remote loopback activate request: this bit position indicates when any of the 8 framers has detected a ds0 remote loopback intermediate activate request (only activate prbs pattern received). this bit position is cleared when the corresponding framer indication is cleared 2 gintdct global intermediate indication for ds0 receive remote loopback deactivate request: this bit position indicates when any of the 8 framers has detected a ds0 remote loopback intermediate deactivate request (only deactivate prbs pattern received). this bit position is cleared when the corresponding framer indication is cleared. 1goverf global overflow indication: this bit position indicates when any of the 8 framers has detected a dpll fifo overflow. this bit position is cleared when the corresponding framer indication is cleared 0 gunderf global underflow indication: this bit position indicates when any of the 8 framers has detected a dpll fifo underflow. this bit position is cleared when the corresponding framer indication is cleared. address (hex) bit symbol description - 184 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 018 7 gmds0rs global receive indication for ds0 receive remote loopback activate request indication mask: when set to 1, this bit disables the hardware inter- rupt for a ds0 remote loopback activate request indication from any of the 8 framers. 6gmds0dc global receive indication for ds0 receive remote loopback deactivate request indication mask: when set to 1, this bit disables the hardware inter- rupt for a ds0 remote loopback deactivate request indication from any of the 8 framers. 5gmds0tp global receive indication for time slot receive out of lock indication mask: when set to 1, this bit disables the hardware interrupt for a time slot out of lock indication for the time slot test pattern from any of the 8 framers. 4gmds0tc global transmit indication for ds0 receive remote loopback sequence complete mask: when set to 1, this bit disables the hardware interrupt for completing a transmit ds0 remote loopback activate/deactivate request indi- cation from any of the 8 framers. 3gmintact global receive intermediate indication for ds0 receive remote loopback activate request indication mask: when set to 1, this bit disables the hard- ware interrupt for a ds0 remote loopback intermediate activate request indi- cation from any of the 8 framers. 2 gmintdct global receive intermediate indication for ds0 receive remote loopback deactivate request indication mask: when set to 1, this bit disables the hardware interrupt for a ds0 remote loopback intermediate deactivate request indication from any of the 8 framers. 1gmoverf global overflow indication mask: when set to 1, this bit disables the hard- ware interrupt for a dpll fifo overflow indication from any of the 8 framers. 0 gmunderf global underflow indication mask: when set to 1, this bit disables the hard- ware interrupt for a dpll fifo underflow from any of the 8 framers. 019 7-0 chr8- chr1 channel activity ds0 remote loopback request or time slot out of lock indication for channels 1 through 8: when a bit is set to 1, it indicates the framer (1 through 8) that caused the global ds0 remote loopback request (receive activate/deactivate, receive activate/deactivate prbs pattern or transmit sequence complete) or out of lock indication (from the prbs/ code word analyzer). address (hex) bit symbol description - 185 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 01a 7 reserved: indeterminate value. 6gais16 global indication for time slot 16 ais: this bit position indicates when any of the 8 framers has detected a time slot 16 ais. this bit position is cleared when the corresponding framer alarm is cleared. 5 gcrce global indication for excessive crc-4 error: this bit position indicates when any of the 8 framers has detected an excessive crc-4 error. this bit posi- tion is cleared when the corresponding framer alarm is cleared 4grai16 global indication for time slot 16 rai: this bit position indicates when any of the 8 framers has detected a time slot 16 rai. this bit position is cleared when the corresponding framer alarm is cleared 3 reserved: indeterminate value. 2 goom16 global indication for out of time slot 16 multiframe alignment: this bit posi- tion indicates when any of the 8 framers has detected a time slot 16 multi- frame alignment error. this bit position is cleared when the corresponding framer alarm is cleared. 1 reserved: indeterminate value. 0gauxp global indication for the auxiliary pattern alarm: this bit position indicates when any of the 8 framers has detected an auxiliary pattern alarm. this bit position is cleared when the corresponding framer alarm is cleared. 01b 7 reserved: write this bit to 0. 6gmais16 global mask for time slot 16 ais indication: this bit disables the hardware interrupt for a time slot 16 ais from any of the 8 framers. 5 gmcrce global mask for excessive crc error indication: this bit disables the hard- ware interrupt for an excessive crc error from any of the 8 framers. 4gmrai16 global mask for time slot 16 rai indication: this bit disables the hardware interrupt for a time slot 16 rai from any of the 8 framers. 3 reserved: write this bit to 0. 2 gmoom16 global mask for out of time slot 16 multiframe alignment indication: this bit disables the hardware interrupt for a time slot 16 multiframe alignment error from any of the 8 framers. 1 reserved: write this bit to 0. 0gmauxp global mask for auxiliary pattern indication: this bit disables the hardware interrupt for an auxiliary pattern alarm from any of the 8 framers. 01c 7-0 chs8- chs1 channel activity line event for channels 1 through 8: when a bit is set to 1, it indicates the framer (1 through 8) that caused the global line indication (ais16, excessive crc, rai16, oomf for time slot 16, or aux. pattern alarms). address (hex) bit symbol description - 186 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers line interface control registers these registers are read/write, except for register 020h, which is read-only unlatched. the control bits in these registers determine the line interface control information flow between the e1fx8 and the external line interface transceivers that support "host mode" control. it also enables the monitor mode for the e1fx8 in the 208-lead package. address (hex) bit symbol description 01d 7 bdcst broadcast command: when set to 1, the two bytes in the command byte and the data output byte are broadcasted to all external line interface transceivers. this is accomplished by forcing all line interface chip select leads (lcsn ) to an active low state. 6 esp enable line interface: when set to 1, a data transfer takes place between the e1fx8 and the selected line interface transceiver (e1chs2-e1chs0). this bit must be first written to a 0 before another data transfer can take place 5 espbmon enable serial port / monitoring port select: when set to 1 and the 208-lead version is used, monclk, monfrm, and mondat use leads lsclk, lsdi, and lsdo respectively. when this bit is set to 0, leads lsclk, lsdi and lsdo are used for line interface transceiver control 4-3 reserved: write these bits to 0. 2-0 e1chs2- e1chs0 external line interface selection: selects the external line interface trans- ceiver, according to the table given below: e1chs2 e1chs1 e1chs0 external transceiver 0 0 0 framer 1 0 0 1 framer 2 0 1 0 framer 3 0 1 1 framer 4 1 0 0 framer 5 1 0 1 framer 6 1 1 0 framer 7 1 1 1 framer 8 01e 7-0 lcb7- lcb0 line interface control command byte: the bits in this register location form the command byte for the external transceivers. this byte is shifted out of this register starting with bit lcb0 first. 01f 7-0 ldo7- ldo0 line interface data output byte: the bits in this register location form the data output byte for the external transceivers. this byte is shifted out of this regis- ter starting with bit ldo0 first. 020 7-0 ldi7- ldi0 line interface data input byte: the bits in this register location form the data input byte from the external transceivers. this byte is shifted into this register starting with bit ldi0 first. - 187 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers monitor control registers these registers select the source of the e1 signal to be monitored, if any, on leads monclk, mondat and monfrm or leads lsclk, lsdo and lsdi in the 208-lead version when control bit espbmon (bit 5) in reg- ister 01dh is set to a 1. they also determine where in the selected framer (transmit, receive line or receive fram- er) the e1 signal is monitored. address (hex) bit symbol description 022 7 monrx monitor receive (or transmit) framer: works in conjunction with the monrf and montr control bits according to the following table. monrx monrf montr action x x 1 monitor data, clock, and framing pulse leads tristated. 0 x 0 monitor transmit framer output 1 0 0 monitor input to receive framer 1 1 0 monitor output from receive framer 6monrf monitor receive framer output: works in conjunction with the monrx and montr control bits according to the table given above. 5montr monitor leads tristate enable: works in conjunction with the monrx and montf control bits according to the table given above. 4-3 reserved: write these bits to 0. 2-0 mfr2- mfr0 monitor framer selection: selects the framer to be monitored according to the table given below. mfr2 mfr1 mfr0 framer to be monitored 0 0 0 framer 1 0 0 1 framer 2 0 1 0 framer 3 0 1 1 framer 4 1 0 0 framer 5 1 0 1 framer 6 1 1 0 framer 7 1 1 1 framer 8 - 188 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers synchronization control registers these read/write registers control the signals placed on clock reference output leads scout1 and scout2 and the source of the one-second clock used for performance monitoring functions. address (hex) bit symbol description 024 7 s18khz synchronization 8 khz reference enable no.1: a 1 selects the synchroniza- tion output clock reference for the framer selected to be an 8 khz rate. a 0 selects the clock reference to be a 2048 khz rate. 6s1ctri synchronization output clock lead tristate enable no. 1: a 1 causes the syn- chronization output clock lead (scout1) to tristate. 5 s1yncen synchronization output clock lead low on los enable no. 1: a 1 enables the synchronization output clock lead (scout1) to go low when a receive line loss of signal is detected. when set to 0, the selected clock continues to be output. 4s1sextb source one-second clock external: when set to 0, the one-second clock source is from lead srget. a 1 selects either a received line clock or the backplane oscillator (from lead bposc) as a clock source and causes lead srget to become an output. see the table below for s1sint. 3s1sint source one-second clock internal selection: this bit is used in conjunction with control bits s1sextb and s1ync2-s1ync0 to select the one-second clock for supporting automatic fdl, shadow counter and performance regis- ter latching, loop up and down code timing, and ds0 loopback activate and deactivate timing. the selection is according to the table below (where x=don?t care): s1sextb s1sint source of one-second clock 0 x external lead sregt 1 0 internal from lead bposc; one-second clock out on srget 1 1 internal from one of the 8 framer line receive clocks as selected by s1ync2 - s1ync0; one-second clock out on srget 2-0 s1ync2- s1ync0 synchronization clock selection no.1: selects the framer from which the clock (2048 khz or 8 khz) is to be monitored according to the table given below. s1ync2 s1ync1 s1ync0 framer to be monitored 0 0 0 framer 1 0 0 1 framer 2 0 1 0 framer 3 0 1 1 framer 4 1 0 0 framer 5 1 0 1 framer 6 1 1 0 framer 7 1 1 1 framer 8 - 189 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 025 7 s28khz synchronization 8 khz reference enable no.2: a 1 selects the synchroniza- tion output clock reference for the framer selected to be an 8 khz rate. a 0 selects the clock reference to be a 2048 khz. 6s2ctri synchronization output clock lead tristate enable no. 2: a 1 causes the syn- chronization output clock lead (scout2) to tristate. 5 s2yncen synchronization output clock lead low on los enable no. 2: a 1 enables the synchronization output clock lead (scout2) to go low when a receive line loss of signal is detected. when set to 0, the selected clock continues to be output. 4-3 reserved: write these bits to 0. 2-0 s2ync2- s2ync0 synchronization clock selection no.2: selects the framer from which the clock (2048 khz or 8 khz) is to be monitored according to the table given below. s2ync2 s2ync1 s2ync0 framer to be monitored 0 0 0 framer 1 0 0 1 framer 2 0 1 0 framer 3 0 1 1 framer 4 1 0 0 framer 5 1 0 1 framer 6 1 1 0 framer 7 1 1 1 framer 8 address (hex) bit symbol description - 190 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers loss of signal detection interval, ones density and code for rai, and ais (trunk conditioning) registers address (hex) bit symbol description 02a 7-0 losi7- losi0 loss of signal detection and recovery interval select: the binary value written to this register selects the number of consecutive missing pulses used to declare loss of signal. the normal range is between 10 and 255. bit 0 is the lsb. this value can be extended via control bit enlosi (bit 7) in register 02bh. this value is also used to set the duration of the recovery interval (see register 02bh). 02b 7 enlosi enable los detection for isdn: when set to 1, the value for losi7-losi0 in register 02ah is multiplied by 16 for the detection period only (this permits up to 2 millisecond period to detect los); the recovery interval remains unchanged. when set to a 0, losi7-losi0 is multiplied by 1. to comply with itu-t g.775 set this bit to 0 and use losi7-losi0 to set the detection win- dow. to comply with itu-t i.431 set this bit to a 1 and losi7-losi0 to 7fh. 6 reserved: write this bit to 0. 5-0 ond5- ond0 ones density loss of signal recovery threshold select: the binary value written to this register selects the minimum number of ones that must occur in the recovery interval set up by register 02ah to recover loss of signal. this value must be less than the value written in register 02ah. for a loss of signal recovery interval value of 255, the recovery threshold value is normally set to 32. bit 0 is the lsb. 02c 7-4 coderai (3-0) code for rai for signaling: when the e1fx8 detects a rai, the value in this register may be substituted for the signaling nibbles forwarded to the signaling highway under control of control bit rx0rai (bit 5) in register x+03h. do not set this code to 0000 as it may mimic the signaling multiframe pattern. control bit rsinv (bit 6) in register x+04h when set to a 1 will invert the value placed on the signaling highway. 3-0 codeais (3-0) code for ais for signaling: when the e1fx8 detects ais, the signaling nib- bles on the signaling highway may have this code substituted in place of the frozen values in the receive signaling ram. control bit rx0aise (bit 7) in register x+03h controls this function. if the a-bits are set to a 1 on the trans- mit signaling highway and control bit tx0aise (bit 1) in register x+06h is set to a 1, this code may be substituted for all the signaling nibbles in time slot 16 in place of the transmit signaling ram values. do not set this code to 0000 as it may mimic the signaling multiframe pattern. control bit rsinv (bit 6) in register x+04h when set to a 1 will invert the value placed on the sig- naling highway for rt0ais (bit 6) in register x+03h or for control bit rx0aise (bit 7) in register x+03h set to a 1 and e1 ais, los or oof is detected. - 191 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit framing pulse (sync) delay control registers the values written in these two read/write registers control the number of clock cycles by which the transmit framing pulse (ttfrmn) and receive framing pulse (rtfrmn) will be delayed relative to the transmit system data (ttdatn) and receive system data (rtdatn), respectively. auxiliary port clock selection and time slot direction registers address (hex) bit symbol description 02e 7-0 rfrm7- rfrm0 receive framing pulse position selection: the control bits in this register determine the location of the framing pulse (rtfrmn) relative to the receive data lead (rtdatn). the clock (rtclkn) and frame pulse (rtfrmn) must be inputs (slip buffer enabled also). when set to 00h, the frame pulse is syn- chronous with bit 8 of the last time slot in transmission mode or the start of frame in data mode, mvip or h-mvip mode. each bit advances the frame pulse one 2.048 mhz clock cycle or eight 16.384 mhz clock cycles. the default value is 00h. 02f 7-0 tfrm7- tfrm0 transmit framing pulse position selection: the control bits in this register determine the location of the framing pulse (ttfrmn) relative to the transmit data lead (ttdatn). the slip buffer must be enabled. the delay is the same as rfrm7-rfrm0 above. each bit advances the frame pulse one 2.048 mhz clock cycle or eight 16.384 mhz clock cycles. the default value is 00h. address (hex) bit symbol description 037 7-5 reserved: write these bits to 0. 4 concaten concatenation control: when set to a 1, a check is made for all auxiliary port transfers such that a contiguous group of time slots will be switched to another contiguous group of time slots with all source time slots from frame n being placed in destination time slots for frame m. when set to a 0, source time slots from frame n will be placed in the defined destination time slots at the next available opportunity without regard for the decisions made for other time slots. 3 tacksel transmit auxiliary port clock selection: this control bit works in conjunction with control bit tadirsel to select the source of taclk and tasync when they are outputs; see below. 2 tadirsel transmit auxiliary port clock direction: when set to a 0 taclk and tasync are inputs. when set to a 1 taclk and tasync are outputs per the follow- ing selection by control bit tacksel above (where x=don?t care). tacksel tadirsel clock selection criteria x 0 taclk and tasync are inputs 0 1 receive line clock is source for taclk and tasync which are outputs; s1ync2-s1ync0 (bits 2-0) in register 024h select the received line. 1 1 lead bposc is source for taclk and tasync which are outputs. - 192 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers auxiliary port receive and transmit data selection registers 037 (cont.) 1 racksel receive auxiliary port clock selection: this control bit works in conjunction with control bit radirsel to select the source of raclk and rasync when they are outputs; see below. 0 radirsel receive auxiliary port clock direction: when set to a 0 raclk and rasync are inputs. when set to a 1 raclk and rasync are outputs per the following selection by control bit racksel above (where x=don?t care). racksel radirsel clock selection criteria x 0 raclk and rasync are inputs 0 1 receive line clock is source for raclk and rasync which are outputs; s1ync2-s1ync0 (bits 2-0) in register 024h select the received line. 1 1 lead bposc is source for raclk and rasync which are outputs. 038 7-0 rdir7- rdir0 receive auxiliary port directionality register for time slots 31 through 0: a 0 on rdirn will connect time slot n on the receive auxiliary port to the output of the receive decoder for the framer and time slot selected control bits rafrseln(2-0) and ratsseln(4-0). a 1 on rdirn will connect time slot n on the receive auxiliary port to the output of the transmit slip buffer for the framer and time slot selected control bits rafrseln(2-0) and ratsseln(4-0). 039 7-0 rdir15- rdir8 03a 7-0 rdir23- rdir9 03b 7-0 rdir31- rdir24 03c 7-0 tdir7- tdir0 transmit auxiliary port directionality register for time slots 31 through 0: a 1 on tdirn will connect time slot n on the transmit auxiliary port in place of the input to the receive slip buffer for the framer and time slot selected con- trol bits tafrseln(2-0) and tatsseln(4-0). a 0 on tdirn will connect time slot n on the transmit auxiliary port in place of the output of the transmit slip buffer for the framer and time slot selected control bits tafrseln(2-0) and tatsseln(4-0). 03d 7-0 tdir15- tdir8 03e 7-0 tdir23- tdir9 03f 7-0 tdir31- tdir24 address (hex) bit symbol description 040 through 05f 7-5 rafrsel31(2-0)- rafrsel0(2-0) receive auxiliary port time slot control register for time slots 31-0: for each time slot, n, on the receive auxiliary port, rafrseln(2-0) selects the framer (000 for framer #1 to 111 for framer #8) and ratsseln(4-0) selects the time slot on the selected framer?s port (00000 for time slot 0 to 11111 for time slot 31). 4-0 ratssel31(4-0)- ratssel0(4-0) address (hex) bit symbol description - 193 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers other control registers (common to all channels) the reserve bits in both registers must be set to 0 for normal device operation. 060 through 07f 7-5 tafrsel31(2-0)- tafrsel0(2-0) transmit auxiliary port time slot control register for time slots 31-0: for each time slot, n, on the transmit auxiliary port, tafrseln(2-0) selects the framer (000 for framer #1 to 111 for framer #8) and tatsseln(4-0) selects the time slot on the selected framer?s port (00000 for time slot 0 to 11111 for time slot 31). 4-0 tatssel31(4-0)- tatssel0(4-0) address (hex) bit symbol description 0fe 7-6 reserved: write these bits to 0. 5 resecksyn reset clock synthesis in e1 mode: this bit when set to a 1 causes the internal clock synthesis block to be reset if control bit disecksyn is set to a 0. if this bit is set to a 0, the internal clock synthesis block if selected by disecksyn also set to a 0. see the table below in the description of disecksyn. 4 disecksyn disable clock synthesis: this bit when set to a 1 causes the internal clock synthesis block to be disabled and an external clock reference needs to be applied to lead dpllref for receive dejitter buffer operation. when this control bit is a 0 the internal clock synthesis block is enabled, generat- ing a reference clock 31.5 times the clock input at lead bposc and output on lead dpllref. this control bit works in conjunction with control bits resecksyn (in this register), recenter and bypass (bits 1 and 0) in register x+161h to control the receive dejitter buffer function (where x=don?t care). 3-0 debval(3-0) signaling debounce value: the value set in this register determines the number of multiframes that any particular signaling nibble must remain the same to be placed in the receive debounce signaling buffer and placed on the signaling highway when signaling debounce is enabled by control bit sigdb (bit 4) in register x+134h being set to a 1. debval(3-0) may not be set to 0h if sigdb is set to 1. address (hex) bit symbol description disecksyn resecksyn bypass function x x 0 e1 dpll bypassed 1 1 0 e1 dpll bypassed and djb powered down 0 0 1 e1 internal dpll 0 1 1 e1 internal dpll held reset 1 1 1 e1 external reference - 194 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers 0ff 7 wg test equipment bpv selection: a 1 enables the decoder to detect coding violations as found in certain test equipment (e.g., wandel and golterman?). a 0 enables the decoder to detect coding violations as found in other types of test equipment (e.g., tberd?). the following table summarizes the two decoding procedures of coding violations: 6-3 reserved: write these bits to 0. 2obt1si observe one-second: when set to 1, the internally selected one-second clock is output on the monfrm lead. otherwise set this bit to 0. 1-0 reserved: write these bits to 0. address (hex) bit symbol description bpv hdb3 1 (wandel and golterman) 0 (tberd) + + or - - 000 (preceding bit changed) 11 0bv or 000v 0000 1010 or 0001 bb00v after odd 1000 1101 bb00v after even 1000 1001 - 195 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers per channel registers framer configuration and control registers the following register descriptions pertain to each of the eight channels (framers). the control bits in the following read/write registers are used to configure the e1fx8 for the various modes of operation on a per channel basis. address (hex) bit symbol description x+00 7 rail dual unipolar/nrz mode selection: a 1 will enable the receive and transmit framer interface for dual unipolar operation, while a 0 enables the receive and transmit framer interface for an nrz interface. 6be hdb3 enable: when set to 1 in dual unipolar mode (rail above set to a 1), the hdb3 transcoder will be enabled. when set to 0 in dual unipolar mode (rail above set to a 1), the ami mode will be selected for the codec. 5rxcp receive clock polarity selection: a 1 enables the receive line signals to be clocked in on rising edges of the line clock (or substitution clock when enabled), while a 0 enables the line input to be clocked in on falling edges of the line clock (rclkn). 4 rxnrz receive nrz data polarity inversion enable: the rail bit above must be set to 0 for this control bit to be enabled. a 1 inverts the polarity of the receive nrz data lead (rnrzn). 3exlos receive external loss of signal enable: enabled when control bit rail is 0 (nrz interface). a 0 enables an external bipolar count to be clocked into the framer on signal lead rscann and counted by the 16 bit bpv counter. a 1 enables an external loss of signal indication to be clocked into the framer. this loss of signal function is treated in the same way as an inter- nally detected los function for alarm propagation and consequent actions. 2elosn receive external loss of signal sense: enabled when control bit rail is a 0, and control bit exlos is a 1. a 0 written to this bit indicates the external input los signal true sense is positive. a 1 indicates the sense is negative. 1enzc enable excess zeros count: the rail bit must be set to 1 for this control bit to take effect. a 1 sets the bpv counter to count an excessive zeros con- dition. for a hdb3 line code, every 4 consecutive zeros will be counted as a single error. for the ami line code, every 16 consecutive zeros will be counted as a single error. 0ts16eic time slot 16 event indication configuration: the time slot 16 event indications (time slot 16 ais, time slot 16 rai, etc. alarms) are combined with normal channel event indications when set to 1. such combination is disabled when set to 0 and the time slot 16 specific events indications will show up at 01ah and 01ch globally and from x+164h through x+168h on a per channel basis, so they can be distinguished from other channel events. - 196 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+01 7 rtfm receive framer transparent control bit: this bit works in conjunction with the ttfm control bit according to the following table (where x=don?t care). rtfm ttfm format selected 1 x receive framer transparent. x 1 transmit framer transparent. 6 ttfm transmit framer transparent control bit: this bit works in conjunction with the rtfm control bit according to the above table. 5bfaa basic frame alignment algorithm: when set to 0, the standard algorithm is selected. when set to 1, the frame hold-off algorithm is selected. note: when in a particular mode, a change in state of this bit will trigger a realignment procedure. the operations section describes the differences between the two modes (algorithms). 4casa channel associated signaling alignment: when set to zero selects the g.732 compatible algorithm. when set to one selects the enhanced algo- rithm. any transition on this signal will trigger a realignment procedure using the selected algorithm. 3 crca automatic crc-4 / non crc-4 interworking: when set to 0 the manual operation is selected. a search for multiframe alignment is started in con- secutive 8 millisecond periods; 2 multiframe alignment patterns separated by a multiple of 2 milliseconds is required to establish multiframe alignment. if alignment is not established, the process is to be repeated; in addition an off line research for basic frame alignment is to be performed. if control bit aags is set to a 1, the rai alarm is set for a single nfas frame and returned to zero. control bit aiw when set to a 0 causes the 400 millisecond timer to monitor the process; if multiframe alignment fails to be found in 400 milliseconds rai is set continuously until multiframe alignment is found. when set to 1 and control bit aiw is set to a 0, the automatic operation for itu-t g.706 is selected. the rai a-bit is set to 0 from a 1 (oof) indicating basic frame alignment and the e-bit is set to a 0 (febe). a search for multi- frame alignment is started in consecutive 8 millisecond periods; 2 multi- frame alignment patterns separated by a multiple of 2 milliseconds is required to establish multiframe alignment. if alignment is not established, the process is to be repeated; in addition an off line re-search for basic frame alignment is to be performed. after 400 milliseconds interworking is to be assumed not to exist if multiframe alignment cannot be found and the e1fx8 will remain in basic frame alignment. if multiframe alignment is found before the 400 millisecond timer expires, interworking is established with the e-bit being set to 1 (set to a 0 only to indicate a crc-4 error in a sub multi- frame). for etsi interworking for ctr-4, no 400 millisecond time out is used, hence set control bit aiw to a 1 (there is no time out if crca = 0). note: when control bit aiw is set to a 1, the 400 millisecond time out does not apply to either algorithm, but the rest of either algorithm is used. any transition on this signal will trigger a realignment procedure using the selected option. once in multiframe alignment only excessive crc-4 errors or loss of basic frame alignment will cause a restart of these algorithms. address (hex) bit symbol description - 197 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+01 (cont.) 2-1 oof1- oof0 out of frame detection criteria: the oof bits determine the out of frame detection criteria according to the following table: oof1 oof0 out of frame detection criteria 0 0 three consecutive fas patterns in error. 0 1 four consecutive fas patterns in error. 1 0 three consecutive fas patterns in error or three con- secutive nfas patterns in error. 1 1 four consecutive fas patterns in error or four consec- utive nfas patterns in error. the fas pattern is defined as x0011011, and the nfas pattern is defined as x1xxxxxx. these two patterns occur in alternating frames. 0aags alternate alarm generation selection: when set to 1, a- and e-bit alarm generation with respect to out of frame and out for multiframe will behave as specified in ets 300 011 (also see itu-t g.704, g.706, 1988). a-bit (rai) will be set each time a re-search for multiframe alignment is performed and the e-bits will be set to 1 unless crc-4 errors are detected after multiframe alignment is achieved. when set to 0, a- and e-bit alarm generation with respect to out of frame and out of multiframe will behave as specified in itu-t g.704, g.706, 1991. in this case the e-bits are set to 0 and the a-bit is set to 1 initially. when basic frame alignment is reached the a-bit is set to 0. the a-bit is only set to 1 again if basic frame alignment is lost due to loss of the time slot 0 fas and nfas codes for excessive crc-4 errors after multiframe alignment is reached (not if an alternate frame position is chosen of if multiframe align- ment can not be reached). the e-bits are set to 1 once multiframe alignment is reached, one e-bit toggling to 0 for each sub-multiframe error detected in a multiframe using the crc-4 check. x+02 7 enais enable receive ais on ais alarm: a 1 enables the generation of ais downstream by forcing the a-bits in the signaling highway to 1 (transmission interface only) when control bit enabit is a 1, or all ones on the data high- way when control bit endbit is a 1 upon the detection of ais. 6 enoof enable receive ais on an oof alarm: a 1 enables the generation of ais downstream by forcing the a-bit in the signaling highway to 1 (transmission highway only) when control bit enabit is a 1, or all ones on the data high- way when control bit endbit is a 1 upon the detection of an oof alarm. 5enlos enable receive ais on an los alarm: a 1 enables the generation of ais downstream by forcing the a-bit in the signaling highway to 1 (transmission interface only) when control bit enabit is a 1, or all ones on the data high- way when control bit endbit is a 1 upon the detection of an los (also external los if enabled) alarm. address (hex) bit symbol description - 198 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+02 (cont.) 4enabit enable receive signaling highway a-bit alarm indication: when set to 1 in the transmission mode, a oof, ais, or los alarm when enabled by the corresponding enable bit (enoof, enais, or enlos) causes the one state for the rtsign receive signaling highway a-bits for the duration of the alarm. 3 endbit enable ais on receive data highway: when set to 1, a e1 oof, ais, or los alarm when enabled by the corresponding enable bit (enoof, enais, or enlos) causes unframed ais to be generated on lead rtdatn for the duration of the alarm. 2rtais send receive system side ais: a 1 will set the a-bit in the signaling high- way (in the transmission mode only) to a 1, when control bit enabit is a 1. a 1 will also cause an unframed ais on the data highway when control bit endbit is a 1. 1 enrai enable rai on receive signaling highway: when set to 1, a receive rai alarm causes the r-bit (bit 3) in time slot 0 of odd frames in the rtsign signaling highway for the transmission mode to be 1 for the duration of the received rai alarm. 0rtrai send receive system side rai indication: a 1 causes the r-bit (bit 3) in time slot 0 of odd frames on the signaling highway for the transmission mode to be 1. x+03 7 rx0aise receive time slot ais enable: a 1 enables time slot ais to be sent when a e1 oof, ais, or los alarm is detected. time slot ais is defined as a spe- cial signaling code abcd=codeais (bits 3-0) in register 02ch. this signal- ing code is inserted into the signaling bits to the signaling highway for all channels. setting codeais =1111 may be used to comply with itu-t g.732 automatically. 6rt0ais sent receive time slot ais: a 1 causes the time slot ais signaling code (abcd=codeais (bits 3-0) in register 02ch) to be inserted into all system side time slot signaling bits. setting codeais = 1111 may be used to meet itu-t g.732 manually on excessive ber as detected by framing word error counts. 5rx0rai receive time slot rai enable: a 1 enables time slot rai to be sent in all system side time slots signaling bits on the signaling highway when a e1 rai alarm is detected. time slot rai is defined as a special signaling code abcd= coderai (bits 7 - 4) in register 02ch. this signaling code is inserted into the signaling bits for all channels. 4rt0rai sent receive time slot rai: a 1 causes the time slot rai signaling code (abcd= coderai (bits 7 - 4) in register 02ch) to be inserted into all sys- tem side time slot signaling bits. address (hex) bit symbol description - 199 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+03 (cont.) 3 enrxnbr enable receive national bit registers: a 1 enables the e1fx8 channel to receive national bits as bytes in registers rsa4(7-0) through rsa8(7-0) and to process alarms for isdn from the national bit sa6. see the sa6 sta- tus register at x+175h, the sa6 counters at x+177h through x+17eh and rsa4(7-0) through rsa8(7-0) in registers x+16fh through x+173h. con- trol bits crcmd1,0 (bits 3 and 2) in register x+07h should be set to a crc-4 mode for rsa4 through rsa8 byte alignment to the multiframe. 2eoocrc enable out of multiframe alarm on loss of crc multiframe: a 1 enables a time slot 0 loss of crc multiframe to cause an out of multiframe alarm. when ts16eic is set, an out of multiframe alarm may also be caused by a time slot 16 loss of multiframe alignment. the following table summarizes the enable bits associated with the out of multiframe alarm. eoocrc eoo16m action 0 0 out of multiframe alarm disabled. 0 1 a time slot 16 loss of multiframe causes an out of multiframe alarm. 1 0 a time slot 0 loss of crc multiframe causes an out of multiframe alarm. 1 1 a time slot 16 loss of multiframe or a time slot 0 loss of crc multiframe causes an out of multiframe alarm. 1eoo16m enable out of multiframe alarm on time slot 16 loss of multiframe: a 1 enables a time slot 16 loss of multiframe to cause an out of ts16 multi- frame alarm. when enabled and ts16eic is set, an out of multiframe alarm may also be caused by time slot 16 loss of multiframe alignment. the table given above summarizes the operation of this bit. 0 enrxauxp enable reception of the auxiliary pattern: when set to a 1, an unframed alternating binary ?10? pattern received 254 or more times on lead rposn/rnegn or rnrzn for 250 microseconds will be detected as auxp (bit 0) in register x+164h. x+04 7 rdinv receive data channels inverted: a 1 inverts the time slot bits in all time slots to the data highway (lead rtdatn); see rdadi below. 6rsinv receive signaling bits inverted: a 1 inverts the abcd signaling bits for all time slots to the signaling highway (lead rtsign); time slot 0 and alarm bits are not inverted. also time slot 16 frame 0 (ts16 multiframe, x0, y, x1 and x2) and a-bits are not inverted. 5 tdinv transmit data channels inverted: a 1 inverts the time slot bits in all time slots from the data or auxiliary highways (lead ttdatn/ttaixn); see tdadi below. 4tsinv transmit signaling bit inverted: a 1 inverts the abcd signaling bits for all time slots from the signaling highway (lead ttsign); time slot 0 and alarm bits are not inverted. also time slot 16 frame 0 (ts16 multiframe, x0, y, x1 and x2) and a-bits are not inverted. address (hex) bit symbol description - 200 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+04 (cont.) 3rdadi receive alternate digit inversion: when set to a 1, the time slots transmit- ted on rtdatn will have bits 2, 4, 6 and 8 inverted. when set to 0, the time slots are not to be inverted. used to supply true a-law from itu-t g.711 a- law. this control bit works in conjunction with control bit rdinv to produce the following options. 2tdadi transmit alternate digit inversion: when set to a 1, the time slots taken from ttdatn will have bits 2, 4, 6 and 8 inverted. when set to 0, the time slots are not to be inverted. used to convert true a-law to itu-t g.711 a- law. this control bit works in conjunction with control bit tdinv to produce the following options. 1enraia enable rai status from a-bit: a 1 enables the detection of the a-bit in ts0 of odd-numbered frames to produce rai status (bit 4 in register x+164h and/or x+10h). 0enraiy enable rai status from y-bit: a 1 enables the detection of the y-bit in ts16 to produce rai status (bit 4 in register x+164h and/or x+10h) if con- trol bit ts16eic is set to a 0. address (hex) bit symbol description rdinv rdadi function on data to rtdatn 0 0 data to the system side is not inverted 0 1 bits 2, 4, 6 and 8 from every time slot to the system side will be inverted. convert from g.711 a-law. 1 0 all bits from every time slot to the system side will be inverted. 1 1 bits 1, 3, 5 and 7 to every time slot from the system side will be inverted. tdinv tdadi function on data from ttdatn 0 0 data from the system side is not inverted 0 1 bits 2, 4, 6 and 8 from every time slot from the system side will be inverted. convert to g.711 a-law. 1 0 all bits from every time slot from the system side will be inverted. 1 1 bits 1, 3, 5 and 7 from every time slot from the system side will be inverted. - 201 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+05 7 pwrd power-down selection: when set to 1, a power-down state is entered by the framer. the forcing function permits a deterministic output to be sent to the line interface unit. this function occurs prior to the selected line encod- ing function. this control bit works in conjunction with the fdat and fpol control bits below, according to the following table (where x=don?t care): pwrd fdat fpol action 0 0 x normal operation 0 1 0 power-up with transmit output forced to 0. 0 1 1 power-up with transmit output forced to 1. 1 0 x do not use. 1 1 0 power-down, transmit output set to 0. 1 1 1 power-down, transmit output set to 1. note: the line clocks are enabled in the power-down mode. 6fdat force transmit data power-down mode: works in conjunction with the pwrd and fpol bits as described in the table above. 5fpol force transmit state upon power-down: works in conjunction with the pwrd and fdat control bits as described in the table above. 4 syfz system freeze: a 1 forces the output line clock tclkn (and rtclkn if out- put) to 0, and gates off rclkn/ rtclkn/ttclkn clocks, until this bit is writ- ten to a 0. 3txcp transmit clock polarity selection: a 1 enables the transmit line signals to be clocked out on rising edges of the line clock (tclkn), while a 0 enables the line signals to be clocked out on falling edges of the line clock. 2 txnrz transmit nrz data polarity inversion enable: the rail bit must be set to 0 for this control bit to be enabled. a 1 inverts the polarity of the transmit nrz data lead (tnrzn). 1enlais enable ais indication on line ais detected: a 1 enables detection of a line ais to cause an ais alarm, as shown in the table below. 0e16ais enable ais indication on ais detected in time slot 16: a 1 enables an ais detected in time slot 16 to cause an ais alarm. when enabled, detec- tion of a line ais may be enabled to cause an ais alarm by setting bit enlais and ts16eic to 1. the following table summarizes the enable bits associated with the ais alarm. e16ais enlais action 0 0 ais alarm detection disabled. 0 1 line ais detected causes an ais alarm (bit 6) in register x+10h set to a 1. 1 0 time slot 16 ais detected causes an ais alarm. 1 1 time slot 16 ais detected or line ais detected causes an ais alarm. address (hex) bit symbol description - 202 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+06 7 txais trans mit ais : a 1 causes an unframed ais (all ones unframed) to be trans- mitted continuously to the line until this bit is written with a 0. 6txrai transmit rai (yellow) alarm indication: a 1 causes an rai (yellow), the remote alarm indication to be transmitted to the line by setting bit 3 in all time slots 0 not carrying the frame alignment pattern (nfas) to a 1. the rai alarm indication will be sent continuously until this bit is written with a 0. please note that the generation of an ais will override the generation of an rai (yellow) alarm indication. 5 extais external ais enable: a 1 enables the generation of an unframed ais to the line when the a-bits in the transmit signaling highway (lead ttsign) in the transmission interface are a 1. 4 extrai external rai (yellow) alarm enable: a 1 enables the generation of an rai (a-bit in time slot 0 nfas frames set to 1) alarm in the transmit direction to the line when the r-bit (bit 3) in time slot 0 in nfas (odd) frames on the transmit signaling highway is a 1 for the transmission mode only. 3entxauxp enable transmission of the auxiliary pattern: when set to a 1, the auxil- iary pattern, an unframed alternating binary ?10? pattern, is transmitted on the e1 line continuously until this bit is written to a 0. 2ulaw mu-law digital milliwatt select: when set to a 1 the mu-law digital milliwatt specified in itu-t g.711 table 6/g.711 is provided for a time slot when tc1cn, tc0cn is set to 11. when set to 0 the a-law digital milliwatt speci- fied in g.711 table 5/g.711 will be provided for a time slot when tc1cn, tc0cn is set to 11. 1 tx0aise transmit time slot ais enable: a 1 enable times slot ais to be inserted into all line side channel signaling bits when the a-bits in the transmission format are detected as a 1. time slot ais is defined as a special signaling code abcd= codeais (bits 3 - 0) in register 02ch. this signaling code replaces the abcd codes normally sent in time slot 16. 0st0ais sent transmit time slot ais: a 1 forces the time slot ais signaling code (abcd= codeais (bits 3-0) in register 02ch) to replace the abcd codes normally sent in time slot 16. x+07 7 tdfme transmit drive framing pulse enable: enabled when control bit rail is a 0 (nrz interface). when this bit is written with a 0, the state written to txdrv determines the state of the tdrvn signal. when this bit is a 1, a framing pulse is provided on the tdrvn lead. 6txdrv transmit drive: enabled when control bit rail is a 0 (nrz interface), and control bit tdfme is a 0. a 1 causes the tdrvn signal to a high, while a 0 causes the tdrvn signal to a low. 5tlmf transmit line multiframe framing indication: enabled when control bit rail is a 0 (nrz interface), and control bit tdfme is a 1. a 1 causes a 2 ms framing pulse to be transmitted on the tdrv lead. a 0 causes a 125 s framing pulse to be transmitted on the tdrvn lead. address (hex) bit symbol description - 203 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+07 (cont.) 4fe1m fractional e1 mode: when set to 1 and the 208-lead version is used, rtauxn, and ttauxn uses leads rtsign, and ttsign respectively. the signaling highways are replaced with gapped clock or channel marker func- tions. when this bit is set to 0, leads rtsign and ttsign remain the signal- ing highways. 3-2 crcmd1, crcmd0 crc framing mode: the crcmd1 and crcmd0 control bits determines the crc framing mode, according to the table given below: crcmd1 crcmd0 crc framing mode 0 0 framed mode. crc-4 enabled. when in sync the e-bits carry the results to the distant end. when out of sync, the e-bits are 0. 0 1 framed mode. crc-4 disabled. si bit used. 1 0 framed mode. crc-4 enabled. when in sync the e-bits carry the results to the distant end. when out of sync, the e-bits are 0. 1 1 framed mode. crc-4 enabled. the e-bits are always set to 1, if aags = 1 (otherwise, e-bits are set to 0 on a oof condition). 1 tais16e transmit time slot 16 ais enable: when set to 1, ais (all ones) is trans- mitted in time slot 16, including the multiframe alignment pattern in frame 0 of a time slot 16 multiframe. ais is defined as all ones. ais is transmitted in time slot 16 until this bit is written with a 0. 0ts16ye generate remote multiframe alarm: when set to 1, a remote multiframe alarm is generated in ts16 (y-bit; bit 6 in time slot 16 in frame 0 of a time slot 16 multiframe) until set to 0. x+08 7 bpcrc4 bypass crc-4 mode: when set to a 1 the receive framer output after the decoder and dejitter buffer is looped to the transmit framer input where one or more of the national bits (sa4 through sa8) may be replaced by being sourced from the transmit facility data link (any control bit in register x+0ch sa4 - sa8 set to a 1), from the signaling highway (control bit bnal in register x+122h set to a 1) or from the transmit sa4-sa8 code registers (tsa4s-tsa8s in register x+e3h set to 0). otherwise, time slots 0 through 31 are passed through intact. crc-4 is updated per itu-t g.706 -1995 annex c, not recalculated. note that the transition of the bpcrc4 bit will cause bit errors. the receive framer may monitor alarms, but control bits autrai and auty behave as if set to 0. note that control bits plp, rlp and llp in register x+107h must be set to 0. 6sa4up sa4 bit update: when set to a 1 and control bit bpcrc4 is set to a 1, the sa4 bit is provided locally by the transmit framer and the crc-4 is updated based on this bit?s new value. when set to a 0 and bpcrc4 is set to a 1, sa4 comes from the received line unchanged. 5sa5up sa5 bit update: when set to a 1 and control bit bpcrc4 is set to a 1, the sa5 bit is provided locally by the transmit framer and the crc-4 is updated based on this bit?s new value. when set to a 0 and bpcrc4 is set to a 1, sa5 comes from the received line unchanged. address (hex) bit symbol description - 204 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+08 (cont.) 4sa6up sa6 bit update: when set to a 1 and control bit bpcrc4 is set to a 1, the sa6 bit is provided locally by the transmit framer and the crc-4 is updated based on this bit?s new value. when set to a 0 and bpcrc4 is set to a 1, sa6 comes from the received line unchanged. 3sa7up sa7 bit update: when set to a 1 and control bit bpcrc4 is set to a 1, the sa7 bit is provided locally by the transmit framer and the crc-4 is updated based on this bit?s new value. when set to a 0 and bpcrc4 is set to a 1, sa7 comes from the received line unchanged. 2sa8up sa8 bit update: when set to a 1 and control bit bpcrc4 is set to a 1, the sa8 bit is provided locally by the transmit framer and the crc-4 is updated based on this bit?s new value. when set to a 0 and bpcrc4 is set to a 1, sa8 comes from the received line unchanged. 1 autrai automatic time slot 0 rai generation: the rai bit is defined as a remote alarm indication, and it is carried in bit 3 in time slot 0 in the (nfas) frames which are not carrying the frame alignment pattern. a 1 enables a loss of basic frame alignment on the receive side (as well as re- attempts to find crc-4 multiframe alignment when control bit aags (bit 0) in register x+01h is set to a 1) to be transmitted as an rai on the transmit side. please note that the microprocessor can generate a remote alarm indication independent of this feature by writing a 1 to control bit txrai (bit 6) in register x+06h. set this bit to 0 when control bit rtfm (bit 7) in regis- ter x+01h = 1. 0auty automatic time slot 16 rai generation: the y-bit is defined as a remote multiframe alarm indication in time slot 16. a 1 enables a loss of multi- frame alignment caused by a loss of basic frame alignment in time slot 0 or a loss of time slot 16 multiframe alignment, as selected by the eoo16m (if control bit ts16eic (bit 0) in register x+00h is set to a 1) control bits (bit 2) in register x+03h, on the receive side to set the y-bit (bit 6) in time slot 16 in frame 0 of the multiframe to be transmitted as a 1. a 0 disables this auto- matic feature. please note that the microprocessor can generate a remote multiframe alarm indication independent of this feature by writing a 1 to con- trol bit ts16ye (bit 0) in register x+07h. set the auty bit to 0 when control bit rtfm (bit 7) in register x+01h = 1. x+0a 7 srst software reset channel: when set to 1, the channel is initialized and held in the reset state until a 0 is written into this bit position. 6rsync receive framer resynchronization: a 1 forces the framer to reset the frame alignment circuit and start a new frame alignment search, treating the present position as a last choice. to start another search, this bit must be first written with a 0, followed by a 1. 5-1 reserved: write these bits to 0. address (hex) bit symbol description - 205 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive fractional e1 channel control registers transmit fractional e1 channel, digital milliwatt, and idle code control registers x+0a (cont.) 0aiw alternate alarm integration window control: when set to a 1, the 400 millisecond timer used to time the end of crc-4/non crc-4 interworking search period or the 400 millisecond timer associated with sending a contin- uous rai when control bit aags (bit 0) in register x+01h is set to a 1 are to be suspended. when this bit is a 0, the 400 millisecond timers are allowed to time out. address (hex) bit symbol description x+1a 7 rchmk receive channel marker: a 1 written into this bit selects a 64 khz channel marker to be output on lead rtauxn for the receive fractional e1 channels, selected by control bits rfch0-rfch31 in registers x+1bh, x+1c, x+1d and x+1e. a 0 selects a 64 kbit/s gapped clock for the fractional channels selected by control bits rfch0-rfch31. 6-0 reserved: write these bits to 0. x+1b 7-0 rfch7- rfch0 receive fractional e1 time slot 7-0 enable: enabled for transmission and data modes only. a 1 written to one or more control bits in this register, causes a 64 khz gapped clock or channel marker to be generated on the rtauxn lead. x+1c 7-0 rfch15- rfch8 receive fractional e1 time slot 15-8 enable: enabled for transmission and data modes only. a 1 written to one or more control bits in this register, causes a 64 khz gapped clock or channel marker to be generated on the rtauxn lead. x+1d 7-0 rfch23- rfch16 receive fractional e1 channels 23-16 enable: enabled for transmission and data modes only. a 1 written to one or more control bits in this register, causes a 64 khz gapped clock or channel marker to be generated on the rtauxn lead. x+1e 7-0 rfch31- rfch24 receive fractional e1 channels 32-25 enable: enabled for transmission and data modes only. a 1 written to one or more control bits in this register, causes a 64 khz gapped clock or channel marker to be generated on the rtauxn lead. address (hex) bit symbol description x+110 7 tchmk transmit channel marker: when this bit is a 1, a channel marker instead of a gapped clock is generated for the transmit fractional e1 channels selected by tc1cc, tc0cc. 6-0 reserved: write these bits to 0. address (hex) bit symbol description - 206 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+111 7 6 5 4 3 2 1 0 tc1c3 tc0c3 tc1c2 tc0c2 tc1c1 tc0c1 tc1c0 tc0c0 transmit control for time slots 31-0: provides the various modes of operation according to the following table. where c is time slots 31-0. tc1cc tc0cc action 0 0 normal operation 0 1 fractional e1 channel; gapped clock or marker on ttauxn; data from ttaixn 1 0 idle code insertion 1 1 a-law or mu-law digital milliwatt note: time slot 0 contents are generated internally; tc1c0, tc0c0 only can generate a gapped clock on ttauxn x+112 7-0 tc1c7- tc0c4 x+113 7-0 tc1c11- tc0c8 x+114 7-0 tc1c15- tc0c12 x+115 7-0 tc1c19- tc0c16 x+116 7-0 tc1c23- tc0c20 x+117 7-0 tc1c27- tc0c24 x+118 7-0 tc1c31- tc0c28 x+119 7-0 idl7- idl0 idle code insertion: the value written to this register by the microproces- sor is transmitted when the idle code feature is selected by the control bits tc1cc-tc0cc in registers x+111h through x+118h. bit 7 represents the first bit to be transmitted. x+161 7-3 reserved: write these bits to 0. 2 attnlm attenuation limit: when set to a 0, the dejitter buffer will not recenter due to an overflow or underflow, but will pass the signal through with the jitter received at its input; no data will be lost or repeated. when set to a 1, the dejitter buffer will recenter on an overflow or underflow; data may be lost or repeated. 1recenter recenter the dejitter buffer: when set to a 1, the dejitter buffer will be recentered. this bit is to be written to a 0 before another recenter command can be given. 0bypass bypass the dejitter buffer: when set to a 0, the dejitter buffer for this framer will be bypassed. address (hex) bit symbol description - 207 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit facility data link control registers these registers control the operation of the 4 to 20 kbit/s hdlc channel that uses the national bits. registers x+124h, x+125h and x+128h are read-only, while register x+127h is write-only. for registers x+124h, x+125h, x+127h and x+128h, a write operation may not be followed by a read operation unless at least 7 cy- cles of sysci occur following the end of the last write cycle. address (hex) bit symbol description x+122 7-6 reserved: write these bits to 0. 5bnal bypass national bits: enabled in the transmission mode. when set to 1, the national bits from the signaling highway (tsigln) in transmission mode only or microprocessor-written bits are used in place of the hdlc data link in the transmit direction. 4-0 reserved: write these bits to 0. x+123 7 ehr enable hdlc receive controller: a 1 enables the hdlc receive controller. after flag detection and zero bit destuffing the receive bytes are written into a receive fifo for microprocessor access. a 0 disables the hdlc controller, and disables the hdlc receive interrupts. 6rhie receive half full interrupt enable: a 1 enables the receive hdlc controller to generate an interrupt when the receive hdlc fifo is half full or has detected an end of message. when set to 0, the hdlc controller generates an interrupt only at the end of the message, or when a fifo overflow has occurred. 5-0 reserved: write these bits to 0. x+124 7-0 rhd7- rhd0 hdlc receive data: a read cycle to this location transfers one byte from the receive hdlc fifo into this location. bit 0 corresponds to the first bit received in the hdlc message. the receive fifo must be cleared by reading this location the number of times indicated by the hdlc fifo depth register (register x+125h) or until the hdlc fifo depth register becomes 0. x+125 7-0 dpt7- dpt0 hdlc fifo depth: this register indicates the number of data bytes present in the receive hdlc fifo. the value is in binary. for example, the value 0000 0000 indicates that the fifo is empty, while a value 0111 1111 indicates that 127 bytes are present. this value is not reset when a new frame is received. the previous frame length is stored in msl6-msl0 (bits 6-0 in register x+128h) which is updated every time a new complete frame (good or errored) is received. this register value is decreased by microprocessor reads of rhd7-rhd0 (register x+124h) only. at initialization this location should read 00h; if it does not, repeated reads of rhd7-rhd0 should be performed until it reads 00h. - 208 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+126 7 eht enable hdlc transmit controller: a 1 enables the hdlc transmit control- ler. the transmitter will send flags when the transmit hdlc fifo is empty. the bytes are formatted into a message when the fifo has bytes present, which is done by loading thd7- thd0 (register x+127h) repeatedly with the byte content of the message to be sent. at the end of the message, a crc is calculated and transmitted. a 0 disables the hdlc controller, clears the trans- mit fifo, and disables the hdlc transmit interrupts. 6tab transmit abort: a 1 causes the hdlc transmit controller to generate and transmit an abort sequence, after the next data byte. this will be followed by clearing the fifo and transmitting continuous flags. 5eom transmit end of message: a 1 instructs the hdlc controller that the trans- mit hdlc fifo contains the last byte in the message. when the fifo has emptied, the crc is calculated and transmitted. when this bit is set to a 0, if the transmit fifo has emptied, an abort character will be transmitted. 4 reserved: write this bit to 0. 3thie transmit half full interrupt enable: this bit controls the this status bit logic to allow interrupts to occur at the fifo half empty or message complete only. a 1 enables the transmit hdlc controller to generate an interrupt when the transmit hdlc fifo is half full or has detected an end of message. when set to 0, the hdlc controller generates an interrupt only at the end of the message, or when a fifo underflowed has occurred. 2-0 reserved: write these bits to 0. x+127 7-0 thd7- thd0 hdlc transmit data: the byte written into this location will be written into the transmit fifo. bit 0 corresponds to the first bit transmitted in an hdlc message byte. x+128 7 reserved: indeterminate value. 6-0 msl6- msl0 message length: this register is loaded with the number of bytes in the last received frame if an end of message, abort, or message received with bad crc event occurs. the microprocessor must read this value before the end of another complete frame is received. x+0c 7-5 reserved: write these bits to 0. 4-0 sa4-sa8 enable sa bits: any or all of these bits can be set high to map the hdlc channel into the combined bandwidth of the national reserved bit positions (sa4-sa8) of time slot 0. address (hex) bit symbol description - 209 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit facility data link status registers these registers are all read/write, except x+0eh, which is read-only. the status bits in the x+0dh registers rep- resent the latched status and interrupt request indications generated by the receive and transmit hdlc link con- trollers and the fifos. the latched event bits are a result of a receive or transmit status indication or interrupt request in the hdlc link status register x+0eh. the bits latch on either the positive transitions, the negative transitions, or both positive and negative transitions of the current status or interrupt request event bits as de- fined by the rise/fall control bits (bits 7 and 6) in the global configuration register 00bh. a latched bit caus- es a hardware interrupt indication when the corresponding mask bit in the hdlc link mask register x+0fh is written with a 0 if the global mask bit gim is also set to 0. the status bits in register x+0eh represent the current (unlatched) status and interrupt request indications generated by the receive and transmit hdlc link controllers and fifos. address (hex) bit symbol description x+0d 7-5 lrhis2- lrhis0 receive hdlc interrupt latched status: the latched bits in this location set on a receive hdlc interrupt status indication. the rise/fall control bits determine the transition on which these bits latch. an interrupt indication occurs when a bit latches, and the corresponding mask bits are disabled. a latched bit is cleared by writing a 0 to it. these latched status bits will change to indicate a corresponding change in rhis2-rhis0 (bits 7-5, in register x+0eh) except when rhis2-rhis0 changes to all zeros, where these latched status bits will retain the previously latched value. 4-3 lrxfs1- lrxfs0 receive hdlc fifo interrupt latched status: the latched bits in this loca- tion set on a receive hdlc fifo status indication. the rise/fall control bits determine the transition on which these bits latch. an interrupt indication will occur when a bit latches, and the corresponding mask bits are disabled. a latched bit is cleared by writing a 0 to it. these latched status bits will change to indicate a corresponding change in rxfs1-rxfs0 (bits 4-3, in register x+0eh) except in the case when rxfs1-rxfs0 changes to all zeros, where these latched status bits will retain the previously latched value. 2-1 ltxfs1- ltxfs0 transmit hdlc fifo interrupt latched status: the latched bits in this location set on a transmit hdlc fifo status indication. the rise/fall con- trol bits determine the transition on which these bits latch. an interrupt indica- tion will occur when a bit latches, and the corresponding mask bits are disabled. a latched bit is cleared by writing a 0 to it. these latched status bits will change to indicate a corresponding change in txfs1-txfs0 (bits 2-1, in register x+0eh) except in the case when txfs1-txfs0 changes to all zeros, where these latched status bits will retain the previously latched value. 0lthis transmit hdlc interrupt latched status: the latched bit in this location set on an transmit hdlc interrupt status indication. the rise/fall control bits determine the transition on which these bits latch. an interrupt indication will occur when a bit latches, and the corresponding mask bit is a disabled. a latched bit is cleared by writing a 0 to it. - 210 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+0e 7-5 rhis2- rhis0 receive hdlc interrupt status: the following table lists the various inter- rupt status indications associated with the hdlc message. these bits are controlled by control bit rhie (bit 6) in register x+123h. note: x=don?t care. 4-3 rxfs1- rxfs0 receive hdlc fifo interrupt status: the following table lists the various fifo status indications associated with the received hdlc fifo. 2-1 txfs1- txfs0 transmit hdlc fifo interrupt status: the following table lists the various fifo status indications associated with the transmit hdlc fifo. 0this transmit hdlc interrupt status: a 1 indicates that the transmit hdlc fifo needs servicing, either because the message is completed, or because the fifo is half full. control bit thie (bit 3) in register x+126h determines if an interrupt is generated at the half full point. address (hex) bit symbol description rhis2 rhis1 rhis0 rhie condition present 0 0 0 x idle condition 0 0 1 x start of message indication 0 1 0 0 valid message received; (crc checked ok, message is < 128 bytes), or the receive fifo needs servicing (full or over- flow). 0 1 0 1 valid message received; (crc checked ok, message is < 128 bytes), or the receive fifo needs servicing (half full or more). 0 1 1 x message received with crc error 1 x x x abort message received rxfs1 rxfs0 condition present 0 0 normal. hdlc fifo less than half full. 0 1 fifo equal to or more than half full 1 0 fifo full 1 1 fifo overflow txfs1 txfs0 condition present 0 0 normal. hdlc fifo equal to or more than half full 0 1 fifo less than half full 1 0 fifo overflow (attempt to write to a full fifo) 1 1 fifo underflow - 211 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit slip buffer control registers these are read/write registers. x+0f 7-5 mrhis2- mrhis0 receive hdlc interrupt mask: when one or more bits are set to a 1, the corresponding bits in the receive hdlc interrupt latched status bits lrhis2- lrhi0 are masked (disabled) from causing an interrupt to occur. 4-3 mrxfs1- mrxfs0 receive hdlc fifo interrupt mask: when one or more bits are set to a 1, the corresponding bits in the receive hdlc fifo interrupt latched status bits lrxfs1-lrxfs0 are masked (disabled) from causing an interrupt to occur. 2-1 mtxfs1- mtxfs0 transmit hdlc fifo interrupt mask: when one or more bits are set to a 1, the corresponding bits in the transmit hdlc fifo interrupt latched status bits ltxfs1-ltxfs0 are masked (disabled) from causing an interrupt to occur. 0mthis transmit interrupt mask: when this bit is set to a 1, the corresponding bit in the transmit interrupt latched status bit lthis is masked (disabled) from caus- ing an interrupt to occur. x+160 7-0 reserved: write these bits to 0. address (hex) bit symbol description x+11b 7 rxcke receive slip buffer clock select: works in conjunction with the rxsbe control bit in this register according to the following table. please note that the slip buffer must be enabled for the mvip and h-mvip interfaces. 6 reserved: write this bit to 0. 5rxsbe receive slip buffer enable: works in conjunction with the rxcke control bit as described in the table above. 4rsr receive slip buffer recenter: toggling rsr from a 0 to a 1 causes the receive slip buffer to recenter. this may cause either an increase or a decrease in delay. the delay value may be read in register bits rxsbd8- rxsbd0 in registers x+23h and x+24h. when set to 0, the receive slip buffer will recenter automatically as needed to prevent overrun or underrun. 3-0 reserved: write these bits to 0. address (hex) bit symbol description rxcke rxsbe action 0 0 invalid combination. 0 1 slip buffer enabled. rtclkn and rtfrmn leads are inputs. 1 0 slip buffer disabled. rtclkn and rtfrmn leads are outputs. 1 1 slip buffer enabled. rtclkn and rtfrmn leads are outputs. - 212 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit slip buffer status registers the following unlatched read-only registers provide status information on the slip buffers. when a common slip error indication is present on status bits slip and lslip (bit 1) in registers x+10h and x+11h, respectively, these registers provide more detail. x+11c 7-6 txc1- txc0 transmit clock source: the transmit clock source is selected according to the following table. 5 txsbe transmit slip buffer enable: a 1 written to this bit position enables the transmit slip buffer, while a 0 causes the slip buffer to be bypassed. 4tsr transmit slip buffer recenter: toggling tsr from a 0 to a 1 causes the receive slip buffer to recenter. this may cause either an increase or a decrease in delay. the delay value may be read in register bits txsbd8- txsbd0 in registers x+25h and x+29h. when set to 0, the transmit slip buffer will recenter automatically as needed to prevent overrun or underrun. 3-0 reserved: write these bits to 0. address (hex) bit symbol description x+15 7-6 rxs1- rxs0 receive slip buffer status: the following table indicates the direction of a receive slip. 5rtslpp remote time slot loopback phase: this is the phase indication that is used for remote time slot loopbacks. a change indicates a slip of only the time slot(s) being remotely looped back has occurred, to prevent a clash between the receive slip buffer write and the transmit slip buffer read. 4-0 reserved: indeterminate value. address (hex) bit symbol description txc1 txc0 action 0 0 back plane oscillator (bposc) 0 1 system clock (ttclkn) 1 0 receive line clock (rclkn) 11not valid rxs1 rxs0 action 0 0 no slips have occurred 0 1 slip buffer overflow. one frame dropped 1 0 slip buffer underflow. one frame repeated 1 1 slip buffer error. two slips in a row - 213 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit slip buffer pointer status registers the following register locations provide receive read and write pointer information, and transmit read and write pointer information, from the receive and transmit slip buffers, respectively. registers x+24h and x+25h are read-only, the rest are read/write but are generally written only by the e1fx8 channel. these pointers are updated at the line rate and are provided for diagnostic purposes; in developing applications, they can be used in conjunction with the system freeze control bit syfz (bit 4) in register x+05h, which will stop the slip buffers and allow for analysis to be performed. please note that the 32 register pairs x+20h/x+21h, x+22h/x+23h, x+26h/x+27h and x+28h/x+29h are constructed for 16-bit word read operations. each pair must always be read in two consecutive read operations, with the even-numbered register being read first, e.g., 220h followed by 221h. doing so will ensure that the read and write side results correspond to the same time instant. if the odd-numbered register is accessed first, data for the read and write sides may correspond to two different time instants. write operations have no such restriction. the slip buffer delay registers (x+23h (bit 6), x+24h, x+25h and x+29h (bit 6)), however, are updated once per frame and tend to change very slowly. they are meant to provide wander information between the write and read clocks and can be used in a microprocessor-based dpll algorithm. x+16 7-6 txs1- txs0 transmit slip buffer status: the following table indicates the direction of a transmit slip. 5ltslpp local time slot loopback phase: this is the phase indication that is used for local time slot loopbacks. a change indicates a slip of only the time slot(s) being locally looped back has occurred, to prevent a clash between the transmit slip buffer write and the receive slip buffer read. 4-0 reserved: indeterminate value. address (hex) bit symbol description x+20 7-0 rwp7- rwp0 receive slip buffer write pointer: the value in this register is the current value of the receive slip buffer write pointer. the value will be between 0 and 255. x+21 7-0 rrp7- rrp0 receive slip buffer read pointer: the value in this register is the current value of the receive slip buffer read pointer. the value will be between 0 and 255. address (hex) bit symbol description txs1 txs0 action 0 0 no slips have occurred 0 1 slip buffer overflow. one frame dropped 1 0 slip buffer underflow. one frame repeated 1 1 slip buffer error. two slips in a row - 214 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+22 7 rwsbs receive slip buffer write side: a 1 indicates that the upper side of the receive slip buffer is currently being written. a 0 indicates the lower side is being written. 6-4 reserved: indeterminate value. 3-0 rwpf3- rwpf0 receive slip buffer write pointer frame: the bits in this location indicate for which frame of the multiframe the receive slip buffer write pointer is being written. bit 0 is the lsb. the value will be between 0 and 15. x+23 7 rrsbs receive slip buffer read side: a 1 indicates that the upper side of the receive slip buffer is currently being read. a 0 indicates the lower side is being read. 6 rxsbd8 receive slip buffer delay (bit 8): the value in this bit indicates the msb of current delay through the receive slip buffer. rxsbd7-rxsbd0 are the lower bits (7-0) of the current delay. 5-4 reserved: write these bits to 0. 3-0 rrpf3- rrpf0 receive slip buffer read pointer frame: the bits in this location indicate for which frame of the multiframe the receive slip buffer read pointer is being read. bit 0 is the lsb. the value will be between 0 and 15. x+24 7-0 rxsbd7- rxsbd0 receive slip buffer delay (bits 7-0): the value in this register indicates the current bits of delay through the receive slip buffer in increments of 1 bits. rxsbd0 is the lsb. x+25 7-0 txsbd7- txsbd0 transmit slip buffer delay (bits 7-0): the value in this register indicates the current bits of delay through the transmit slip buffer in increments of 1 bits. txsbd0 is the lsb. x+26 7-0 twp7- twp0 transmit slip buffer write pointer: the value in this register is the current value of the transmit slip buffer write pointer. the value will be between 0 and 255. x+27 7-0 trp7- trp0 transmit slip buffer read pointer: the value in this register is the current value of the transmit slip buffer read pointer. the value will be between 0 and 255. x+28 7 twsbs transmit slip buffer write side: a 1 indicates that the upper side of the transmit slip buffer is currently being written. a 0 indicates the lower side is being written. 6-4 reserved: indeterminate value. 3-0 twpf3- twpf0 transmit slip buffer write pointer frame: the bits in this location indicate for which frame of the multiframe the transmit slip buffer write pointer is being written. bit 0 is the lsb. the value will be between 0 and 15. address (hex) bit symbol description - 215 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive slip buffer control registers the control bits in the following read/write registers are used to enable or disable (freeze) the receive slip buffer locations for the system highway, and to allow the microprocessor to write in service codes and idle codes. these registers control the receive slip buffer write actions from the receive line port. control bits rdec, when written to 0, can freeze the individual time slots in the slip buffer for analysis or for microprocessor writing to force specific time slot codes to be output on the system side data highway (where c = 1 - 31). x+29 7 trsbs transmit slip buffer read side: a 1 indicates that the upper side of the transmit slip buffer is currently being read. a 0 indicates the lower side is being read. 6 txsbd8 transmit slip buffer delay (bit 8): the value in this bit indicates the msb of current delay through the transmit slip buffer. txsbd7-txsbd0 are the lower bits (7-0) of the current delay. 5-4 reserved: write these bits to 0. 3-0 trpf3- trpf0 transmit slip buffer read pointer frame: the bits in this location indicate for which frame of the multiframe the transmit slip buffer read pointer is being read. bit 0 is the lsb. the value will be between 0 and 15. address (hex) bit symbol description x+3a 7-3 reserved: write these bits to 0. 2-0 rx2s- rx0s receive time slot 16 spare bits select: bits rx2s-rx0s correspond to the spare bits x2-x0 in bit positions 8, 7 and 5 in time slot 16 of frame 0 in the time slot 16 multiframe. when a bit is set to 1, the corresponding spare bit received in time slot 16 is sent to the receive signaling highway via a buffer (when operating in transmission mode). when set to 0, the receive spare bit in the multiframe is disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of the bit in the buffer may be rewritten by the microprocessor for sending to the receive signaling highway. x+3b 7 rsis receive international bits (si) select: when set to 1, the two international bits received from the line (in bit 1 of time slot 0 in alternating fas and nfas frames) are sent to the receive signaling highway (when operating in trans- mission mode), and to the data highway, via a buffer. when set to 0, the received international bits are disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of these bits in the buffer may be rewritten by the microprocessor. 6-5 reserved: write these bits to 0. 4-0 rsa4s- rsa8s receive national bits select: when set to 1, the national bits received from the e1 line are sent to the receive signaling highway (when operating in a transmission mode), via a buffer. when set to 0, the national bits are sent to the signaling highway from the last value in the receive buffer; this value is writable by the microprocessor. address (hex) bit symbol description - 216 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+3c 7-1 rde7- rde1 receive time slot enable for time slots 7-1: when a bit in this register is set to 1, the corresponding received time slot is written into the receive slip buffer. the time slot is then read from the receive slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the receive slip buffer. instead, the micropro- cessor may write the value of the time slot into the receive slip buffer and this value will be read from the receive slip buffer for the receive data highway. bit 7 is assigned to receive time slot 7. the receive slip buffers are located in registers x+47h-x+41h (frame 1) and x+67h-x+61h (frame 2). 0 reserved: write this bit to 0. x+3d 7-0 rde15- rde8 receive time slot enable for time slots 15-8: when a bit in this register is set to 1, the corresponding received time slot is written into the receive slip buffer. the time slot is then read from the receive slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the receive slip buffer. instead, the micropro- cessor may write the value of the time slot into the receive slip buffer and this value will be read from the receive slip buffer for the receive data highway. bit 7 is assigned to receive time slot 15. the receive slip buffers are located in registers x+4fh-x+48h (frame 1) and x+6fh-x+68h (frame 2). x+3e 7-0 rde23- rde16 receive time slot enable for time slots 23-16: when a bit in this register is set to 1, the corresponding received time slot is written into the receive slip buffer. the time slot is then read from the receive slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the receive slip buffer. instead, the micropro- cessor may write the value of the time slot into the receive slip buffer and this value will be read from the receive slip buffer for the receive data highway. bit 7 is assigned to receive time slot 23. the receive slip buffers are located in registers x+57h-x+50h (frame 1) and x+77h-x+70h (frame 2). x+3f 7-0 rde31- rde24 receive time slot enable for time slots 31-24: when a bit in this register is set to 1, the corresponding received time slot is written into the receive slip buffer. the time slot is then read from the receive slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the receive slip buffer. instead, the micropro- cessor may write the value of the time slot into the receive slip buffer and this value will be read from the receive slip buffer for the receive data highway. bit 7 is assigned to receive time slot 31. the receive slip buffers are located in registers x+5fh-x+58h (frame 1) and x+7fh-x+78h (frame 2). address (hex) bit symbol description - 217 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive slip buffer frame storage registers the bits in these read/write registers are the received time slots that are present in the receive slip buffer including time slot 0. address (hex) bit symbol description x+40 7-0 rfas receive time slot 0 fas buffer: the time slot bits for time slot 0 in frames carrying the frame alignment pattern (fas, frame 1) are written into this loca- tion from the line when control bit ts0fz (bit 5) in register x+134h is set to a 0 and is not slip buffered. when ts0fz is set to a 1, time slot 0 may or may not contain a fas pattern and this location is slip buffered. if rtfm is set to a 0, it will contain either fas or nfas, if rtfm is set to a 1 this location may contain any data. when control bit rsis (bit 7) in register x+3bh, is written with a 0, the state of the international bit from the line cannot be written into the buffer, and the buffer value is frozen. the microprocessor can now write the value of the international bit for receive time slot 0 to the system. the other bits represent the frame alignment sequence in time slot 0. x+41- x+5f 7-0 rts1- rts31 for frame 1 receive slip buffer time slots 1-31 storage locations - frame 1: regis- ter locations x+41h-x+5fh represent frame 1 in the two-frame slip buffer for the data highway. the register locations for a time slot are enabled when the corresponding receive time slot enable bits (rde1-rde31) are written with a 1. when one or more control bits in rde1-rde31 are written with a 0, the corresponding receive time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer locations are frozen. the microprocessor can now write an idle or service code to the correspond- ing buffer location. please note that both frame locations in the slip buffer must be written for a time slot (see x+61h to x+7fh below). x+60 7-0 rnfas receive time slot 0 nfas buffer: the time slot 0 bits for frames not car- rying the frame alignment pattern (nfas, frame 2) are written into this loca- tion from the line when control bit ts0fz (bit 5) in register x+134h is set to a 0 and is not slip buffered. when ts0fz is set to a 1, time slot 0 may or may not contain a nfas pattern and this location is slip buffered. if rtfm is set to a 0, it will contain either fas or nfas, if rtfm is set to a 1 this location may contain any data. when control bit rsis (bit 7) and rsa4s-rsa8s (bits 4-0) in register x+3bh are set to 0, the states of the corresponding international bit and national bits from the line cannot be written into the buffer, and the corresponding buffer value is frozen. the microprocessor can now write the value of the corresponding international bit and national bits for receive time slot 0 to the system. x+61- x+7f 7-0 rts1- rts31 for frame 2 receive slip buffer time slots 1-31 storage locations - frame 2: regis- ter locations x+61h-x+7fh represent frame 2 in the two-frame slip buffer for the data highway. the register locations for a time slot are enabled when the corresponding receive time slot enable bits (rde1-rde31) are written with a 1. when one or more control bits in rde1-rde31 are written with a 0, the corresponding receive time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer locations are frozen. the microprocessor can now write an idle or service code to the correspond- ing buffer location. please note that both frame locations in the slip buffer must be written for a time slot (see x+41h-x+5fh above). - 218 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit slip buffer control registers the control bits in the following read/write registers are used to enable or disable (freeze) the transmit slip buffer locations for the transmit line, and to allow the microprocessor to write in service codes and idle codes. these registers control the transmit slip buffer write actions from the system side transmit port. control bits tdec, when written to 0, can freeze the individual time slots in the slip buffer for analysis or for microprocessor writing to force specific time slot codes to be output on the transmit line (where c = 1 - 31). address (hex) bit symbol description x+e2 7-3 reserved: write these bits to 0. 2-0 tx2s- tx0s transmit time slot 16 spare bits select: bits tx2s-tx0s correspond to the spare bits x2-x0 in bit positions 8, 7 and 5 in time slot 16 of frame 0 in the time slot 16 multiframe. when a bit is set to 1, the corresponding spare bit in time slot 16 from the transmit signaling highway is transmitted via a buffer. when set to 0, the transmit spare bit is disabled from being written into the buffer, and the value sitting in the buffer will frozen. the value of the bit in the buffer may be rewritten by the microprocessor for sending to the line. x+e3 7 tsis transmit international bits (si) select: this bit is enabled when the crc framing mode bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are equal to 01. when set to 1, the two international bits for frames 1 and 2 in time slot 0 from the signaling highway are sent as the transmit bits via a buffer. when set to 0, the transmit international bits are disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of these bits in the buffer may be rewritten by the microprocessor for sending to the line. the buffer locations are registers x+90h (fas, frame 1) and x+b0h (nfas, frame 2). 6-5 reserved: write these bits to 0. 4-0 tsa4s- tsa8s transmit national bits (sa4-sa8) select: bit 4 corresponds to the transmit sa4 bit in time slot 0 of nfas frames. when a bit is set to 1, the correspond- ing transmit national bit of frame 2 received in time slot 0 on the transmit sig- naling highway (when in transmission mode) is transmitted via a buffer when control bit bnal (bit 5) in register x+122h is a 1. when a bit is set to 0, the corresponding transmit national bit from the signaling highway is written into the buffer, but is disabled from being written into the line and the value sitting in the buffer is frozen. the value of the national bit is taken from the transmit sa4 - sa8 code registers for sending to the line. x+e4 7-1 tde7- tde1 transmit time slot enable for time slots 7-1: when a bit in this register is set to 1, the corresponding transmit time slot from the transmit data highway is written into the transmit slip buffer. the time slot is then read from the trans- mit slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding time slot from the transmit data highway will not be writ- ten into the transmit slip buffer. instead, the microprocessor writes the value of the time slot into the transmit slip buffer and this value will be read from the transmit slip buffer for the transmit line. bit 7 is assigned to transmit time slot 7. the transmit slip buffers are located in registers x+97h - x+91h (frame 1) and x+b7h -x+b1h (frame 2). 0 reserved: write this bit to 0. - 219 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+e5 7-0 tde15- tde8 transmit time slot enable for time slots 15-8: when a bit in this register is set to 1, the corresponding transmit time slot from the transmit data high- way is written into the transmit slip buffer. the time slot is then read from the transmit slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding time slot from the transmit data highway will not be written into the transmit slip buffer. instead, the microprocessor writes the value of the time slot into the transmit slip buffer and this value will be read from the transmit slip buffer for the transmit line. bit 7 is assigned to transmit time slot 15. the transmit slip buffers are located in registers x+9fh - x+98h (frame 1) and x+bfh -x+b8h (frame 2). x+e6 7-0 tde23- tde16 transmit time slot enable for time slots 23-16: when a bit in this register is set to 1, the corresponding transmit time slot from the transmit data high- way is written into the transmit slip buffer. the time slot is then read from the transmit slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding time slot from the transmit data highway will not be written into the transmit slip buffer. instead, the microprocessor writes the value of the time slot into the transmit slip buffer and this value will be read from the transmit slip buffer for the transmit line. bit 7 is assigned to transmit time slot 23. the transmit slip buffers are located in registers x+a7h - x+a0h (frame 1) and x+c7h -x+c0h (frame 2). x+e7 7-0 tde31- tde24 transmit time slot enable for time slots 31-24: when a bit in this register is set to 1, the corresponding transmit time slot from the transmit data high- way is written into the transmit slip buffer. the time slot is then read from the transmit slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding time slot from the transmit data highway will not be written into the transmit slip buffer. instead, the microprocessor writes the value of the time slot into the transmit slip buffer and this value will be read from the transmit slip buffer for the transmit line. bit 7 is assigned to transmit time slot 31. the transmit slip buffers are located in registers x+afh - x+a8h (frame 1) and x+cfh -x+c8h (frame 2). address (hex) bit symbol description - 220 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit slip buffer frame storage registers the bits in these read/write registers are the time slots to be transmitted and come from the transmit slip buffer. address (hex) bit symbol description x+90 7-0 tfas transmit time slot 0 fas buffer: the time slot bits for time slot 0 in frames carrying the frame alignment pattern (fas, frame 1) are written into this location from the signaling highway when a transmission mode is selected, and from the data highway when the 2 mbit/s mvip mode or 8 mbit/s h-mvip mode is selected. when control bit tsis (bit 7) in register x+e3h is written with a 0, the state of the international bit from the system interface (signaling highway or data highway) cannot be written into the buffer and the buffer value is frozen. the microprocessor can now write the value of the international bit for transmit time slot 0 that will be sent to the line. x+91- x+af 7-0 tts1- tts31 for frame 1 transmit slip buffer time slots 1-31 storage locations - frame 1: reg- ister locations x+91h-x+afh represent frame 1 in the two-frame slip buffer from the data highway. the register locations for a time slot are enabled when the corresponding transmit time slot enable bits (tde1-tde31) are written with a 1. when one or more control bits in tde1-tde31 are written with a 0, the corresponding transmit time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer loca- tions are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. please note that both frame locations in the slip buffer must be written for a time slot (see x+b1h-x+cfh below). x+b0 7-0 tnfas transmit time slot 0 nfas buffer: the time slot bits for time slot 0 in frames not carrying the frame alignment pattern (nfas, frame 2) are written into this location from the signaling highway when a transmission mode is selected, and from the data highway when the 2 mbit/s mvip mode or 8 mbit/s h-mvip mode is selected. when control bit tsis and tsa4s-tsa8s are set to 0, the states of the corresponding international bit and national bits from the system interface (signaling highway or data highway) cannot be written into the line from the buffer, although the buffer continues updat- ing. the microprocessor can now write the values of the corresponding international bit for transmit time slot 0 into the code registers x+169h through x+16dh that will be sent to the line. x+b1- x+cf 7-0 tts1- tts31 for frame 2 transmit slip buffer time slots 1-31 storage locations - frame 2: reg- ister locations x+b1h-x+cfh represent frame 2 in the two-frame slip buffer from the data highway. the register locations for a time slot are enabled when the corresponding transmit time slot enable bits (tde1-tde31) are written with a 1. when one or more control bits in tde1-tde31 are written with a 0, the corresponding transmit time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer loca- tions are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. please note that both locations in the slip buffer must be written for a time slot (see x+91h-x+afh above). - 221 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit signaling state control registers the following read/write registers control how signaling is to be handled in the e1fx8. address (hex) bit symbol description x+134 7-6 typ1- typ0 signaling type selection: the following table lists the signaling selection formats in the transmit and receive directions that are controlled by bits typ1 and typ0. typ1 typ0 signaling type 0 0 time slot 16 assigned as a clear channel. 0 1 time slot 16 assigned for cas. abcd bits carried. abcd = 0000 from the transmit signaling highway (evaluated after tsinv application) or from stored loca- tions in the transmit signaling ram sent on the e1 line in time slot 16 as 1111 to prevent mimics of the time slot 16 multiframe alignment pattern. 1 0 time slot 16 assigned for cas. abcd bits carried. 1 1 not used the time slot 16 multiframe alignment pattern is generated for all options except typ1, typ0 is equal to 00. when typ1, typ0 is equal to 00, time slot 16 is slip buffered as a telephone channel. when typ1, typ0 is not equal to 00, time slot 16 uses the signaling buffers. 5ts0fz time slot 0 slip buffer freeze: when set to a 0 the receive slip buffer frame storage registers at x+40h and x+60h are used to store fas and nfas as received from the line. when set to a 1 time slot 0 is treated as a telephone channel and slip buffered as time slots 1 through 31. 4sigdb signaling debounce: when set to a 1, the signaling bits are debounced. each signaling nibble must be the same for the number of consecutive multi- frames determined by control bits debval(3-0) (bits 3-0) in register 0feh before being placed in the signaling buffer or placed on the signaling highway. 3 sigien signaling interrupt enabled: when set to a 1, the change of state after debouncing (control bit sigdb set to a 1) of any of the received signaling bits for time slots which have signaling enabled (rsen = 1) causes an interrupt if not masked. note control bits typ0, typ1 can not equal 00. 2 reserved: write this bit to 0. 1 rxsfz receive signaling freeze: a 1 causes a freeze of the signaling states in the receive signaling buffer, by disabling writing to the buffer from the line. the contents of the frozen state are sent on the signaling highway repeatedly for the duration of the signaling freeze. the microprocessor is permitted to write the signaling states. 0txsfz transmit signaling freeze: a 1 causes a freeze of the signaling states in the transmit signaling buffer, by disabling writing to the buffer from the system. the contents of the transmit signaling buffer are repeatedly transmitted for the duration of the signaling freeze. the microprocessor is permitted to write the signaling states for call control, trunk conditioning, etc. - 222 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling control registers the bits in these read/write registers control the receive signaling for telephone channels 1 through 30. address (hex) bit symbol description x+e8 7-0 rse8- rse1 receive signaling enable for channels 8-1: when a bit in this register is set to 1, the receive signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the receive signaling buffers from the receive line, and are inserted into the receive signaling high- way. when set to 0, the signaling states in the receive signaling buffers are frozen. the ability to internally write the signaling bits from the line into the receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the receive signaling registers. bit 7 is the enable bit for telephone channel 8 or time slot 8. signaling information for telephone channel c is carried in time slot c. x+e9 7-0 rse16- rse9 receive signaling enable for channels 16-9: when a bit in this register is set to 1, the receive signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the receive signaling buffers from the receive line, and are inserted into the receive signaling high- way. when set to 0, the signaling states in the receive signaling buffers are frozen. the ability to internally write the signaling bits from the line into the receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the receive signaling registers. bit 7 is the enable bit for channel 16. signaling information for telephone channel c is carried in time slot c, except for channel 16, which is carried in time slot 17. x+ea 7-0 rse24- rse17 receive signaling enable for channels 24-17: when a bit in this register is set to 1, the receive signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the receive signaling buffers from the receive line, and are inserted into the receive signaling high- way. when set to 0, the signaling states in the receive signaling buffers are frozen. the ability to internally write the signaling bits from the line into the receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the receive signaling registers. bit 7 is the enable bit for channel 24. signaling information for telephone channel c is carried in time slot c+1. x+eb 7-6 reserved: write these bits to 0. 5-0 rse30- rse25 receive signaling enable for channels 30-25: when a bit in this register is set to 1, the receive signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the receive signaling buffers from the receive line, and are inserted into the receive signaling high- way. when set to 0, the signaling states in the receive signaling buffers are frozen. the ability to internally write the signaling bits from the line into the receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the receive signaling registers. bit 5 is the enable bit for channel 30. signaling information for telephone channel c is carried in time slot c+1. - 223 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling state debounce registers (debounce buffer) the contents of these locations are raw received values always for rx0, ry, rx1 and rx2. if sigdb is set to a 0, signaling bits an - dn are raw received values. if sigdb is set to a 1, debounced values for an - dn are stored in these registers. address (hex) bit symbol description x+80 7-4 rsigmas received signaling multiframe alignment signal: the bits in this regis- ter contains the states of the received multiframe alignment pattern (time slot 16 bits 1-4 in frame 0) in the receive signaling buffer. this pattern is normally 0000. bit 7 is received bit 1. 3-0 rx0, ry, rx1, rx2 received signaling spare bits and remote alarm bit: bits 3, 1 and 0 in this register contains the states of the received x0, x1, x2 bits (spare bits) in time slot 16, which correspond to bits 5, 7, and 8 in frame 0 of the time slot 16 multiframe. the ry bit (bit 2) is defined as the loss of multiframe indication bit and is carried in bit 6 in frame 0 of the time slot 16 multi- frame. x+81 7-4 3-0 ra1-rd1 ra16-rd16 receive a1-d1 and a16-d16 signaling bits: the signaling bits in this register are the states of the received a1 to d1 bits and the a16 to d16 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 1 (time slot 1) and 16 (time slot 17). bit 7 is the a1 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1 (where c is the channel number, from 1 to 30). when the corresponding enable bit is written with a 0, a sig- naling freeze occurs, and the value read in a bit position in this register rep- resents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 1 and 16 in this register. x+82 7-4 3-0 ra2-rd2 ra17-rd17 receive a2-d2 and a17-d17 signaling bits: the signaling bits in this register are the states of the received a2 to d2 bits and the a17 to d17 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 2 (time slot 2) and 17 (time slot 18). bit 7 is the a2 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 2 and 17 in this register. - 224 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+83 7-4 3-0 ra3-rd3 ra18-rd18 receive a3-d3 and a18-d18 signaling bits: the signaling bits in this register are the states of the received a3 to d3 bits and the a18 to d18 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 3 (time slot 3) and 18 (time slot 19). bit 7 is the a3 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 3 and 18 in this register. x+84 7-4 3-0 ra4-rd4 ra19-rd19 receive a4-d4 and a19-d19 signaling bits: the signaling bits in this register are the states of the received a4 to d4 bits and the a19 to d19 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 4 (time slot 4) and 19 (time slot 20). bit 7 is the a4 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 4 and 19 in this register. x+85 7-4 3-0 ra5-rd5 ra20-rd20 receive a5-d5 and a20-d20 signaling bits: the signaling bits in this register are the states of the received a5 to d5 bits and the a20 to d20 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 5 (time slot 5) and 20 (time slot 21). bit 7 is the a5 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 5 and 20 in this register. x+86 7-4 3-0 ra6-rd6 ra21-rd21 receive a6-d6 and a21-d21 signaling bits: the signaling bits in this register are the states of the received a6 to d6 bits and the a21 to d21 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 6 (time slot 6) and 21 (time slot 22). bit 7 is the a6 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 6 and 21 in this register. address (hex) bit symbol description - 225 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+87 7-4 3-0 ra7-rd7 ra22-rd22 receive a7-d7 and a22-d22 signaling bits: the signaling bits in this register are the states of the received a7 to d7 bits and the a22 to d22 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 7 (time slot 7) and 22 (time slot 23). bit 7 is the a7 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 7 and 22 in this register. x+88 7-4 3-0 ra8-rd8 ra23-rd23 receive a8-d8 and a23-d23 signaling bits: the signaling bits in this register are the states of the received a8 to d8 bits and the a23 to d23 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 8 (time slot 8) and 23 (time slot 24). bit 7 is the a8 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 8 and 23 in this register. x+89 7-4 3-0 ra9-rd9 ra24-rd24 receive a9-d9 and a24-d24 signaling bits: the signaling bits in this register are the states of the received a9 to d9 bits and the a24 to d24 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 9 (time slot 9) and 24 (time slot 25). bit 7 is the a9 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 9 and 24 in this register. x+8a 7-4 3-0 ra10-rd10 ra25-rd25 receive a10-d10 and a25-d25 signaling bits: the signaling bits in this register are the states of the received a10 to d10 bits and the a25 to d25 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 10 (time slot 10) and 25 (time slot 26). bit 7 is the a10 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 10 and 25 in this register. address (hex) bit symbol description - 226 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+8b 7-4 3-0 ra11-rd11 ra26-rd26 receive a11-d11 and a26-d26 signaling bits: the signaling bits in this register are the states of the received a11 to d11 bits and the a26 to d26 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 11 (time slot 11) and 26 (time slot 27). bit 7 is the a11 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 11 and 26 in this register. x+8c 7-4 3-0 ra12-rd12 ra27-rd27 receive a12-d12 and a27-d27 signaling bits: the signaling bits in this register are the states of the received a12 to d12 bits and the a27 to d27 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 12 (time slot 12) and 27 (time slot 28). bit 7 is the a12 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 12 and 27 in this register. x+8d 7-4 3-0 ra13-rd13 ra28-rd28 receive a13-d13 and a28-d28 signaling bits: the signaling bits in this register are the states of the received a13 to d13 bits and the a28 to d28 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 13 (time slot 13) and 28 (time slot 29). bit 7 is the a13 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 13 and 28 in this register. x+8e 7-4 3-0 ra14-rd14 ra29-rd29 receive a14-d14 and a29-d29 signaling bits: the signaling bits in this register are the states of the received a14 to d14 bits and the a29 to d29 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 14 (time slot 14) and 29 (time slot 30). bit 7 is the a14 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 14 and 29 in this register. address (hex) bit symbol description - 227 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling state registers (active buffer 1) this is one of two active buffers used for signaling debounce. the contents are valid if control bit sigdb is set to a 1. this buffer contains the most recent signaling nibble received from the e1 line. x+8f 7-4 3-0 ra15-rd15 ra30-rd30 receive a15-d15 and a30-d30 signaling bits: the signaling bits in this register are the states of the received a15 to d15 bits and the a30 to d30 bits in the receive signaling buffer. the bits correspond to the abcd signal- ing bits carried in time slot 16 for channels 15 (time slot 15) and 30 (time slot 31). bit 7 is the a15 signaling bit value. please note that a receive sig- naling state is written into the receive signaling buffer when the correspond- ing channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 15 and 30 in this register. address (hex) bit symbol description x+137 7-4 rrsigmas received signaling multiframe alignment signal: the bits in this reg- ister contain the temporary states of the received multiframe alignment pattern (time slot 16 (bits 1-4) in frame 0) in the receive signaling buffer. this pattern is normally 0000. bit 7 is received bit 1. 3-0 rrx0, rry, rrx1, rrx2 received signaling spare bits and remote alarm bit: bits 3, 1 and 0 in this register contain the temporary states of the received x0, x1, x2 bits (spare bits) in time slot 16, which correspond to bits 5, 7, and 8 in frame 0 of the time slot 16 multiframe. the rry bit (bit 2) is defined as the loss of multiframe indication bit and is carried in bit 6 in frame 0 of the time slot 16 multiframe. x+138 7-4 3-0 rra1-rrd1 rra16-rrd16 receive a1-d1 and a16-d16 signaling bits: the signaling bits in this register are the states of the received a1 to d1 bits and the a16 to d16 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 1 (time slot 1) and 16 (time slot 17). bit 7 is the a1 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1 (where c is the channel number, from 1 to 30). when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 1 and 16 in this register. address (hex) bit symbol description - 228 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+139 7-4 3-0 rra2-rrd2 rra17-rrd17 receive a2-d2 and a17-d17 signaling bits: the signaling bits in this register are the states of the received a2 to d2 bits and the a17 to d17 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 2 (time slot 2) and 17 (time slot 18). bit 7 is the a2 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 2 and 17 in this register. x+13a 7-4 3-0 rra3-rrd3 rra18-rrd18 receive a3-d3 and a18-d18 signaling bits: the signaling bits in this register are the states of the received a3 to d3 bits and the a18 to d18 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 3 (time slot 3) and 18 (time slot 19). bit 7 is the a3 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 3 and 18 in this register. x+13b 7-4 3-0 rra4-rrd4 rra19-rrd19 receive a4-d4 and a19-d19 signaling bits: the signaling bits in this register are the states of the received a4 to d4 bits and the a19 to d19 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 4 (time slot 4) and 19 (time slot 20). bit 7 is the a4 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 4 and 19 in this register. x+13c 7-4 3-0 rra5-rrd5 rra20-rrd20 receive a5-d5 and a20-d20 signaling bits: the signaling bits in this register are the states of the received a5 to d5 bits and the a20 to d20 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 5 (time slot 5) and 20 (time slot 21). bit 7 is the a5 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 5 and 20 in this register. address (hex) bit symbol description - 229 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+13d 7-4 3-0 rra6-rrd6 rra21-rrd21 receive a6-d6 and a21-d21 signaling bits: the signaling bits in this register are the states of the received a6 to d6 bits and the a21 to d21 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 6 (time slot 6) and 21 (time slot 22). bit 7 is the a6 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 6 and 21 in this register. x+13e 7-4 3-0 rra7-rrd7 rra22-rrd22 receive a7-d7 and a22-d22 signaling bits: the signaling bits in this register are the states of the received a7 to d7 bits and the a22 to d22 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 7 (time slot 7) and 22 (time slot 23). bit 7 is the a7 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 7 and 22 in this register. x+13f 7-4 3-0 rra8-rrd8 rra23-rrd23 receive a8-d8 and a23-d23 signaling bits: the signaling bits in this register are the states of the received a8 to d8 bits and the a23 to d23 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 8 (time slot 8) and 23 (time slot 24). bit 7 is the a8 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 8 and 23 in this register. x+140 7-4 3-0 rra9-rrd9 rra24-rrd24 receive a9-d9 and a24-d24 signaling bits: the signaling bits in this register are the states of the received a9 to d9 bits and the a24 to d24 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 9 (time slot 9) and 24 (time slot 25). bit 7 is the a9 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 9 and 24 in this register. address (hex) bit symbol description - 230 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+141 7-4 3-0 rra10-rrd10 rra25-rrd25 receive a10-d10 and a25-d25 signaling bits: the signaling bits in this register are the states of the received a10 to d10 bits and the a25 to d25 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 10 (time slot 10) and 25 (time slot 26). bit 7 is the a10 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 10 and 25 in this register. x+142 7-4 3-0 rra11-rrd11 rra26-rrd26 receive a11-d11 and a26-d26 signaling bits: the signaling bits in this register are the states of the received a11 to d11 bits and the a26 to d26 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 11 (time slot 11) and 26 (time slot 27). bit 7 is the a11 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 11 and 26 in this register. x+143 7-4 3-0 rra12-rrd12 rra27-rrd27 receive a12-d12 and a27-d27 signaling bits: the signaling bits in this register are the states of the received a12 to d12 bits and the a27 to d27 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 12 (time slot 12) and 27 (time slot 28). bit 7 is the a12 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 12 and 27 in this register. x+144 7-4 3-0 rra13-rrd13 rra28-rrd28 receive a13-d13 and a28-d28 signaling bits: the signaling bits in this register are the states of the received a13 to d13 bits and the a28 to d28 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 13 (time slot 13) and 28 (time slot 29). bit 7 is the a13 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 13 and 28 in this register. address (hex) bit symbol description - 231 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+145 7-4 3-0 rra14-rrd14 rra29-rrd29 receive a14-d14 and a29-d29 signaling bits: the signaling bits in this register are the states of the received a14 to d14 bits and the a29 to d29 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 14 (time slot 14) and 29 (time slot 30). bit 7 is the a14 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 14 and 29 in this register. x+146 7-4 3-0 rra15-rrd15 rra30-rrd30 receive a15-d15 and a30-d30 signaling bits: the signaling bits in this register are the states of the received a15 to d15 bits and the a30 to d30 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 15 (time slot 15) and 30 (time slot 31). bit 7 is the a15 signaling bit value. please note that a receive signaling state is written into the receive signaling buffer when the corresponding channel enable bit rsec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits to the receive signaling highway for channels 15 and 30 in this register. address (hex) bit symbol description - 232 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive signaling state match count registers this is one of two active buffers used for signaling debounce. the contents are valid if control bit sigdb is set to a 1. this buffer contains the four bit current match count (saturating) for each of the 30 signaling nibbles. address (hex) bit symbol description x+147 7-0 reserved: indeterminate value. x+148 7-4 3-0 rsnm1 rsnm16 match counts for signaling nibbles for telephone channel 1 and 16: this register contains two four bit saturating counters, rsnm1 and rsnm16. rsnm1 is set to 0h if signaling is not enabled (rse1, bit 0 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra1-rrd1 (bits 7-4 of register x+138h). rsnm1 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm1 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra1-rd1 (bits 7-4 of register x+81h). rsnm16 is set to 0h if signaling is not enabled (rse16, bit 7 of register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra16-rrd16 (bits 3-0 of register x+138h). rsnm16 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm16 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra16 - rd16 (bits 3 -0 of register x+81h). x+149 7-4 3-0 rsnm2 rsnm17 match counts for signaling nibbles for telephone channel 2 and 17: this register contains two four bit saturating counters, rsnm2 and rsnm17. rsnm2 is set to 0h if signaling is not enabled (rse2, bit 1 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra2-rrd2 (bits 7-4 of register x+139h). rsnm2 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm2 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra2-rd2 (bits 7-4 of register x+82h). rsnm17 is set to 0h if signaling is not enabled (rse17, bit 0 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra17 - rrd17 (bits 3-0 of register x+139h). rsnm17 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm17 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra17-rd17 (bits 3-0 of register x+82h). - 233 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+14a 7-4 3-0 rsnm3 rsnm18 match counts for signaling nibbles for telephone channel 3 and 18: this register contains two four bit saturating counters, rsnm3 and rsnm18. rsnm3 is set to 0h if signaling is not enabled (rse3, bit 2 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra3-rrd3 (bits 7-4 of register x+13ah). rsnm3 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm3 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra3-rd3 (bits 7-4 of register x+83h). rsnm18 is set to 0h if signaling is not enabled (rse18, bit 1 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra18-rrd18 (bits 3-0 of register x+13ah). rsnm18 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm18 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra18-rd18 (bits 3-0 of register x+83h). x+14b 7-4 3-0 rsnm4 rsnm19 match counts for signaling nibbles for telephone channel 4 and 19: this register contains two four bit saturating counters, rsnm4 and rsnm19. rsnm4 is set to 0h if signaling is not enabled (rse4, bit 3 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra4-rrd4 (bits 7-4 of register x+13bh). rsnm4 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm4 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra4-rd4 (bits 7-4 of register x+84h). rsnm19 is set to 0h if signaling is not enabled (rse19, bit 2 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra19 - rrd19 (bits 3- 0 of register x+13bh). rsnm19 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm19 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra19-rd19 (bits 3-0 of register x+84h). address (hex) bit symbol description - 234 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+14c 7-4 3-0 rsnm5 rsnm20 match counts for signaling nibbles for telephone channel 5 and 20: this register contains two four bit saturating counters, rsnm5 and rsnm20. rsnm5 is set to 0h if signaling is not enabled (rse5, bit 4 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra5-rrd5 (bits 7-4 of register x+13ch). rsnm5 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm5 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra5-rd5 (bits 7-4 of register x+85h). rsnm20 is set to 0h if signaling is not enabled (rse20, bit 3 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra20-rrd20 (bits 3-0 of register x+13ch). rsnm20 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm20 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra20-rd20 (bits 3-0 of register x+85h). x+14d 7-4 3-0 rsnm6 rsnm21 match counts for signaling nibbles for telephone channel 6 and 21: this register contains two four bit saturating counters, rsnm6 and rsnm21. rsnm6 is set to 0h if signaling is not enabled (rse6, bit 5 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra6-rrd6 (bits 7-4 of register x+13dh). rsnm6 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm6 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra6-rd6 (bits 7-4 of register x+86h). rsnm21 is set to 0h if signaling is not enabled (rse21, bit 4 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra2 -rrd21 (bits 3- 0 of register x+13dh). rsnm21 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm21 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra21-rd21 (bits 3-0 of register x+86h). address (hex) bit symbol description - 235 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+14e 7-4 3-0 rsnm7 rsnm22 match counts for signaling nibbles for telephone channel 7 and 22: this register contains two four bit saturating counters, rsnm7 and rsnm22. rsnm7 is set to 0h if signaling is not enabled (rse7, bit 6 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra7-rrd7 (bits 7-4 of register x+13eh). rsnm7 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm7 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra7-rd7 (bits 7-4 of register x+87h). rsnm22 is set to 0h if signaling is not enabled (rse22, bit 5 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra22-rrd22 (bits 3-0 of register x+13eh). rsnm22 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm22 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra22-rd22 (bits 3-0 of register x+87h). x+14f 7-4 3-0 rsnm8 rsnm23 match counts for signaling nibbles for telephone channel 8 and 23: this register contains two four bit saturating counters, rsnm8 and rsnm23. rsnm8 is set to 0h if signaling is not enabled (rse8, bit 7 in register x+e8h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra8-rrd8 (bits 7-4 of register x+13fh). rsnm8 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm8 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra8 - rd8 (bits 7-4 of register x+88h). rsnm23 is set to 0h if signaling is not enabled (rse23, bit 6 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra23-rrd23 (bits 3-0 of register x+13fh). rsnm23 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm23 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra23-rd23 (bits 3-0 of register x+88h). address (hex) bit symbol description - 236 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+150 7-4 3-0 rsnm9 rsnm24 match counts for signaling nibbles for telephone channel 9 and 24: this register contains two four bit saturating counters, rsnm9 and rsnm24. rsnm9 is set to 0h if signaling is not enabled (rse9, bit 0 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra9-rrd9 (bits 7-4 of register x+140h). rsnm9 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm9 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra9-rd9 (bits 7-4 of register x+89h). rsnm24 is set to 0h if signaling is not enabled (rse24, bit 7 in register x+eah is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra24-rrd24 (bits 3-0 of register x+140h). rsnm24 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm24 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signal- ing state debounce buffer ra24-rd24 (bits 3-0 of register x+89h). x+151 7-4 3-0 rsnm10 rsnm25 match counts for signaling nibbles for telephone channel 10 and 25: this register contains two four bit saturating counters, rsnm10 and rsnm25. rsnm10 is set to 0h if signaling is not enabled (rse10, bit 1 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra10-rrd10 (bits 7-4 of register x+141h). rsnm10 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm10 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra10-rd10 (bits 7-4 of register x+8ah). rsnm25 is set to 0h if signaling is not enabled (rse25, bit 0 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra25-rrd25 (bits 3-0 of register x+141h). rsnm25 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm25 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra25-rd25 (bits 3-0 of register x+8ah). address (hex) bit symbol description - 237 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+152 7-4 3-0 rsnm11 rsnm26 match counts for signaling nibbles for telephone channel 11 and 26: this register contains two four bit saturating counters, rsnm11 and rsnm26. rsnm11 is set to 0h if signaling is not enabled (rse11, bit 2 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra11-rrd11 (bits 7-4 of register x+142h). rsnm11 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm11 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra11-rd11 (bits 7-4 of register x+8bh). rsnm26 is set to 0h if signaling is not enabled (rse26, bit 1 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra26-rrd26 (bits 3-0 of register x+142h). rsnm26 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm26 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra26-rd26 (bits 3-0 of register x+8bh). x+153 7-4 3-0 rsnm12 rsnm27 match counts for signaling nibbles for telephone channel 12 and 27: this register contains two four bit saturating counters, rsnm12 and rsnm27. rsnm12 is set to 0h if signaling is not enabled (rse12, bit 3 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra12-rrd12 (bits 7-4 of register x+143h). rsnm12 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm12 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra12-rd12 (bits 7-4 of register x+8ch). rsnm27 is set to 0h if signaling is not enabled (rse27, bit 2 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra27-rrd27 (bits 3-0 of register x+143h). rsnm27 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm27 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra27-rd27 (bits 3-0 of register x+8ch). address (hex) bit symbol description - 238 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+154 7-4 3-0 rsnm13 rsnm28 match counts for signaling nibbles for telephone channel 13 and 28: this register contains two four bit saturating counters, rsnm13 and rsnm28. rsnm13 is set to 0h if signaling is not enabled (rse13, bit 4 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra13-rrd13 (bits 7-4 of register x+144h). rsnm13 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm13 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra13-rd13 (bits 7-4 of register x+8dh). rsnm28 is set to 0h if signaling is not enabled (rse28, bit 3 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra28-rrd28 (bits 3-0 of register x+144h). rsnm28 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm28 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra28-rd28 (bits 3-0 of register x+8dh). x+155 7-4 3-0 rsnm14 rsnm29 match counts for signaling nibbles for telephone channel 14 and 29: this register contains two four bit saturating counters, rsnm14 and rsnm29. rsnm14 is set to 0h if signaling is not enabled (rse14, bit 5 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra14-rrd14 (bits 7-4 of register x+145h). rsnm14 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm14 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra14-rd14 (bits 7-4 of register x+8eh). rsnm29 is set to 0h if signaling is not enabled (rse29, bit 4 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra29-rrd29 (bits 3-0 of register x+145h). rsnm29 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm29 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra29-rd29 (bits 3-0 of register x+8eh). address (hex) bit symbol description - 239 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit signaling control registers the bits in these read/write registers control the transmit signaling for telephone channels 1 through 30. x+156 7-4 3-0 rsnm15 rsnm30 match counts for signaling nibbles for telephone channel 15 and 30: this register contains two four bit saturating counters, rsnm15 and rsnm30. rsnm15 is set to 0h if signaling is not enabled (rse15, bit 6 in register x+e9h is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra15-rrd15 (bits 7-4 of register x+146h). rsnm15 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm15 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra15-rd15 (bits 7-4 of register x+8fh). rsnm30 is set to 0h if signaling is not enabled (rse30, bit 5 in register x+ebh is set to a 0) or the signaling nibble just received does not match the value stored in the signaling state active buffer 1 rra30-rrd30 (bits 3-0 of register x+146h). rsnm30 is incremented if the signaling nibble just received matches the value stored in the signaling state active buffer 1. if rsnm30 is equal to or greater than global threshold debval(3-0) (bits 3-0) in register 0feh, the nibble stored in the signaling state active buffer 1 is transferred to the signaling state debounce buffer ra30-rd30 (bits 3-0 of register x+8fh). address (hex) bit symbol description x+ec 7-0 tse8- tse1 transmit signaling enable for channels 8-1: when a bit in this register is set to 1, the transmit signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the transmit signaling buffers from the transmit signaling highway, and are inserted into the transmit line. when set to 0, the signaling states in the transmit signaling buffer are fro- zen. the ability to internally write the signaling bits from the transmit signaling highway into the transmit signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit signaling regis- ters. bit 7 is the enable bit for channel 8. signaling information for telephone channel c is carried in time slot c. x+ed 7-0 tse16- tse9 transmit signaling enable for channels 16-9: when a bit in this register is set to 1, the transmit signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the transmit signaling buffers from the transmit signaling highway, and are inserted into the transmit line. when set to 0, the signaling states in the transmit signaling buffer are fro- zen. the ability to internally write the signaling bits from the transmit signaling highway into the transmit signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit signaling regis- ters. bit 7 is the enable bit for channel 16. signaling information for telephone channel c is carried in time slot c, except for channel 16, which is carried in time slot 17. address (hex) bit symbol description - 240 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+ee 7-0 tse24- tse17 transmit signaling enable for channels 24-17: when a bit in this register is set to 1, the transmit signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the transmit signaling buffers from the transmit signaling highway, and are inserted into the transmit line. when set to 0, the signaling states in the transmit signaling buffer are fro- zen. the ability to internally write the signaling bits from the transmit signaling highway into the transmit signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit signaling regis- ters. bit 7 is the enable bit for channel 24. signaling information for telephone channel c is carried in time slot c+1. x+ef 7-6 reserved: write these bits to 0. 5-0 tse30- tse25 transmit signaling enable for channels 30-25: when a bit in this register is set to 1, the transmit signaling bits for the corresponding telephone channel are enabled. the abcd signaling bits are written into the transmit signaling buffers from the transmit signaling highway, and are inserted into the transmit line. when set to 0, the signaling states in the transmit signaling buffer are fro- zen. the ability to internally write the signaling bits from the transmit signaling highway into the transmit signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit signaling regis- ters. bit 5 is the enable bit for channel 30. signaling information for telephone channel c is carried in time slot c+1. address (hex) bit symbol description - 241 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit signaling state registers these read/write registers contain the transmit signaling nibbles for telephone channels 1 through 30, plus the time slot 16 multiframe bits and the spare/remote alarm bits. address (hex) bit symbol description x+d0 7-4 tsigmas transmit signaling multiframe alignment signal: the bits in this register contain the states of the transmit multiframe alignment pattern (time slot 16 bits 1-4 in frame 0) in the transmit signaling buffer. this pattern is normally 0000. bit 7 is transmitted bit 1. 3-0 tx0, ty, tx1, tx2 transmit signaling spare bits and remote alarm bit: bits 3, 1 and 0 in this register contain the states of the transmit x0, x1, x2 bits (spare bits) in time slot 16, which are carried in bits 5, 7, and 8 of frame 0 in the multi- frame. the ty bit (bit 2) is defined as the loss of multiframe indication bit and is carried in bit 6 in frame 0 of the multiframe. x+d1 7-4 3-0 ta 1 - t d 1 ta 1 6 - t d 1 6 transmit a1-d1 and a16-d16 signaling bits: the signaling bits in this register are the a1 to d1 and a16 to d16 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 1 (time slot 1) and 16 (time slot 17). bit 7 is the a1 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 1 and 16 in this register. x+d2 7-4 3-0 ta 2 - t d 2 ta 1 7 - t d 1 7 transmit a2-d2 and a17-d17 signaling bits: the signaling bits in this register are the a2 to d2 and a17 to d17 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 2 (time slot 2) and 17 (time slot 18). bit 7 is the a2 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding enable bit tsec is written with a 1. when the corresponding chan- nel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 2 and 17 in this register. x+d3 7-4 3-0 ta 3 - t d 3 ta 1 8 - t d 1 8 transmit a3-d3 and a18-d18 signaling bits: the signaling bits in this register are the a3 to d3 and a18 to d18 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 3 (time slot 3) and 18 (time slot 19). bit 7 is the a3 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 3 and 18 in this register. - 242 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+d4 7-4 3-0 ta 4 - t d 4 ta 1 9 - t d 1 9 transmit a4-d4 and a19-d19 signaling bits: the signaling bits in this register are the a4 to d4 and a19 to d19 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 4 (time slot 4) and 19 (time slot 20). bit 7 is the a4 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 4 and 19 in this register. x+d5 7-4 3-0 ta 5 - t d 5 ta 2 0 - t d 2 0 transmit a5-d5 and a20-d20 signaling bits: the signaling bits in this register are the a5 to d5 and a20 to d20 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 5 (time slot 5) and 20 (time slot 21). bit 7 is the a5 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 5 and 20 in this register. x+d6 7-4 3-0 ta 6 - t d 6 ta 2 1 - t d 2 1 transmit a6-d6 and a21-d21 signaling bits: the signaling bits in this register are the a6 to d6 and a21 to d21 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 6 (time slot 6) and 21 (time slot 22). bit 7 is the a6 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 6 and 21 in this register. x+d7 7-4 3-0 ta 7 - t d 7 ta 2 2 - t d 2 2 transmit a7-d7 and a22-d22 signaling bits: the signaling bits in this register are the a7 to d7 and a22 to d22 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 7 (time slot 7) and 22 (time slot 23). bit 7 is the a7 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 7 and 22 in this register. address (hex) bit symbol description - 243 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+d8 7-4 3-0 ta 8 - t d 8 ta 2 3 - t d 2 3 transmit a8-d8 and a23-d23 signaling bits: the signaling bits in this register are the a8 to d8 and a23 to d23 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 8 (time slot 8) and 23 (time slot 24). bit 7 is the a8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 8 and 23 in this register. x+d9 7-4 3-0 ta 9 - t d 9 ta 2 4 - t d 2 4 transmit a9-d9 and a24-d24 signaling bits: the signaling bits in this register are the a9 to d9 and a24 to d24 signaling bits written into the sig- naling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 9 (time slot 9) and 24 (time slot 25). bit 7 is the a9 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corre- sponding channel enable bit tsec is written with a 1. when the correspond- ing enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that cor- respond to channels 9 and 24 in this register. x+da 7-4 3-0 ta 1 0 - t d 1 0 ta 2 5 - t d 2 5 transmit a10-d10 and a25-d25 signaling bits: the signaling bits in this register are the a10 to d10 and a25 to d25 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 10 (time slot 10) and 25 (time slot 26). bit 7 is the a10 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 10 and 25 in this register. x+db 7-4 3-0 ta 1 1 - t d 1 1 ta 2 6 - t d 2 6 transmit a11-d11 and a26-d26 signaling bits: the signaling bits in this register are the a11 to d11 and a26 to d26 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 11 (time slot 11) and 26 (time slot 27). bit 7 is the a11 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 11 and 26 in this register. address (hex) bit symbol description - 244 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+dc 7-4 3-0 ta 1 2 - t d 1 2 ta 2 7 - t d 2 7 transmit a12-d12 and a27-d27 signaling bits: the signaling bits in this register are the a12 to d12 and a27 to d27 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 12 (time slot 12) and 27 (time slot 28). bit 7 is the a12 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 12 and 27 in this register. x+dd 7-4 3-0 ta 1 3 - t d 1 3 ta 2 8 - t d 2 8 transmit a13-d13 and a28-d28 signaling bits: the signaling bits in this register are the a13 to d13 and a28 to d28 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 13 (time slot 13) and 28 (time slot 29). bit 7 is the a13 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 13 and 28 in this register. x+de 7-4 3-0 ta 1 4 - t d 1 4 ta 2 9 - t d 2 9 transmit a14-d14 and a29-d29 signaling bits: the signaling bits in this register are the a14 to d14 and a29 to d29 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 14 (time slot 14) and 29 (time slot 30). bit 7 is the a14 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 14 and 29 in this register. x+df 7-4 3-0 ta 1 5 - t d 1 5 ta 3 0 - t d 3 0 transmit a15-d15 and a30-d30 signaling bits: the signaling bits in this register are the a15 to d15 and a30 to d30 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 15 (time slot 15) and 30 (time slot 31). bit 7 is the a15 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit tsec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 15 and 30 in this register. address (hex) bit symbol description - 245 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers e1 line status registers these registers are read/write, except for registers x+10h and x+164h, which are read-only unlatched. the status bits in the x+11h and x+165h registers represent the latched status indications generated by the chan- nel alarms. the bits latch on either the positive transition, the negative transition, or both transitions of the cur- rent status or interrupt request event bits in register x+10h/x+164h as defined by the rise/fall control bits (bits 7 and 6) in the global configuration register 00bh. a latched bit will cause a hardware interrupt indication when the global interrupt mask bit gim (bit 5) in register 00bh, and the corresponding mask bit in the mask registers, x+14h and x+166h are both written with a 0 and the associated global mask bits in registers 012h and 01bh are set to 0. the bits in register x+10h and x+165h represent the current (unlatched) alarm status. a latched status bit is reset by writing a 0 into the latched bit position, or by the rising edge of the one-second pulse (from sregt, bposc or rclkn) when the performance monitoring/fault monitoring feature is enabled. this feature activates the shadow registers x+12h, x+13h, x+167h and x+168h, and it is enabled by writing a 1 to control bit srgen (bit 3) in the global configuration register 00bh. address (hex) bit symbol description x+10 7 los loss of signal alarm indication: this bit position is used to indicate a unlatched line loss of signal alarm indication. a 1 is a true state. when control bit rail (bit 7) in register x+00h is set to a 1 loss of signal is a consecutive string of bit periods when no pulses are detected on either lead rposn or lead rnegn as defined by control bits losi7-losi0 in register 02ah, ond5- ond0 and enlosi in register 02bh. in addition, los may also be generated in nrz mode (rail = 0) as controlled by control bits exlos and elosn (bits 3 and 2) in register x+00h and rxfs (bit 1) in register x+1ffh by a sig- nal on rscann input lead. 6ais ais alarm indication (unlatched): a 1 indicates that a line alarm indication signal (ais) (and/or an ais in time slot 16 if control bit ts16eic is set to a 1) has been detected. control bit enlais enables a line ais alarm. control bit e16ais enables a receive time slot 16 ais alarm. control bit enaisi (bit 5) in register 00ch determines the detection criteria for ais. when enaisi is set to 0,a line ais is detected when the received line signal has two or less zeros in each of two consecutive double-frame periods (512 bits). recovery occurs when each of two consecutive double-frame periods contain three or more zeros after frame alignment has been detected. this is itu-t g.775 compliant. when enaisi is set to 1,a line ais is detected when the received line signal has two or less zeros in a single double-frame period (512 bits). recovery occurs when a single double-frame period contains three or more zeros after frame alignment has been detected. an ais in time slot 16 is detected when the received time slot has detected three or less zeros in each of two consecutive multiframe periods. recovery occurs when each of two consecutive multiframe periods contains four or more zeros or when the mul- tiframe alignment signal has been detected. 5oof out of frame (oof) alarm (unlatched): a 1 indicates that an out of frame alarm has been detected. the alarm is programmed using the oof1 and oof0 control (bits 2 and 1) in register x+01h. the e1fx8 supports two recovery schemes, with or without the crc-4 check. see the operations sec- tion for more details. - 246 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+10 (cont.) 4rai remote alarm indication (rai) (unlatched): a 1 indicates that the received rai bit is a 1 for four or more consecutive frames in which it is carried. the rai bit is bit 3 in time slot 0, in those alternate (nfas) frames that are not carrying the frame alignment pattern. if control bit ts16eic (bit 0) in register x+00h is set to a 1, the occurrence of three of the y-bits of time slot 16 set to a 1 will also cause this bit to be set. recovery occurs when the rai bit is 0 for four (nfas) or three (y-bit) or more consecutive frames in which it is carried. 3cfa change in frame alignment (cfa) indication (unlatched): a 1 indicates that the frame alignment circuit has detected a change in the frame alignment pattern, only after frame alignment has been regained. 2oofm out of multiframe alignment (oofm) alarm (unlatched): a 1 indicates that time slot 16 multiframe alignment has been lost (if control bit ts16eic (bit 0) in register x+00h is set to a 1) and/or a crc-4 multiframe alignment has also been lost. control bit eoocrc (bit 2) in register x+03h enables a loss of crc-4 multiframe alignment alarm. control bit eoo16m (bit 1) in reg- ister x+03h enables a ts16 multiframe alarm. 1slip slip indication (unlatched): this bit reflects the current status of the trans- mit/receive slip buffer with respect to a slip being executed in the previous 125 micro- seconds. a 1 is true state. 0 schg signaling change of state indication: this bit position is used to indicate a change of state of any signaling bit when control bit sigien (bit 3) in register x+134h is set to a 1. a 1 is a true state. x+11 7 llos latched loss of signal (los): this bit position latches when there is a transition in the unlatched bit los in register x+10h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 6lais latched ais: this bit position latches when there is a transition in the unlatched bit ais in register x+10h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corre- sponding global mask bit, an interrupt is generated. this bit is cleared by writ- ing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 5loof latched out of frame (oof): this bit position latches when there is a tran- sition in the unlatched bit oof in register x+10h. this bit is set on the transi- tion set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control regis- ter or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). address (hex) bit symbol description - 247 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+11 (cont.) 4lrai latched remote alarm indication (rai): this bit position latches when there is a transition in the unlatched bit rai in register x+10h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 3lcfa latched change in frame alignment alarm: this bit position latches when there is a transition in the unlatched bit cfa in register x+10h. this bit is set on the transition set by the rise bit in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control reg- ister or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 2 loofm latched out of multiframe alignment (oofm): this bit position latches when there is a transition in the unlatched bit oofm in register x+10h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is gener- ated. this bit is cleared by writing a 0 into this bit position or by the one-sec- ond pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 1lslip latched slip indication: this bit position latches when there is a transition in the unlatched bit slip in register x+10h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corre- sponding global mask bit, an interrupt is generated. this bit is cleared by writ- ing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 0 lschg latched signaling change of state indication: this bit position latches when there is a transition in the unlatched bit schg in register x+10h. this bit is set on the transition set by the rise bit in register 00bh. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow reg- ister feature is enabled (global control bit srgen set to a 1). address (hex) bit symbol description - 248 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+12 7 plos loss of signal alarm one-second error indication: enabled when control bit srgen (bit 3) in register 00bh is a 1, otherwise this bit is held to 0. this bit is set to 1 when a loss of signal alarm indication has been detected in the last one-second interval. 6pais ais one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an ais alarm indication in register x+10h has been detected in the last one-second interval. 5 poof out of frame one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an out of frame alarm indication in register x+10h has been detected in the last one- second interval. 4prai rai (yellow) alarm one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a rai (yellow) alarm indication in register x+10h has been detected in the last one- second interval. 3pcfa change in frame alignment indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a change in frame alignment indication in register x+10h has been detected in the last one-second interval. 2poofm out of multiframe alignment (oofm) one-second error: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an out of multiframe alignment indication in register x+10h has been detected in the last one-second interval. 1pslip transmit or receive slip one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a slip indication in register x+10h has been detected in the last one- second interval. 0 pschg signaling change of state one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a signaling change of state indication in register x+10h has been detected in the last one-second interval. address (hex) bit symbol description - 249 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+13 7 flos loss of signal alarm persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a loss of signal alarm indication is active, but did not become active in the last one-second interval. 6fais ais persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-sec- ond interval when an ais alarm indication is active, but did not become active in the last one-second interval. 5 foof out of frame persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when an out of frame alarm indication in register x+10h is active, but did not become active in the last one-second interval. 4frai rai (yellow) alarm persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when a rai (yellow) alarm indication in register x+10h is active, but did not become active in the last one-second interval. 3fcfa change in frame alignment persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when a change in frame alignment alarm indication in register x+10h is active, but did not become active in the last one-second interval. 2 foofm out of multiframe alignment (oofm) persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval if the oofm alarm in register x+10h is active, but did not become active in the last one-second interval. 1fslip transmit or receive slip persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when a slip is active, but did not become active in the last one-second interval. 0fschg transmit slip persistent one-second error indication: enabled when con- trol bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when a signaling change of state in register x+10h is active, but did not become active in the last one-second interval. address (hex) bit symbol description - 250 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+14 7 mlos loss of signal alarm indication interrupt mask bit: when set to 1, the latched loss of signal alarm indication is masked from providing a hardware interrupt. 6mais ais alarm indication interrupt mask bit: when set to 1, the latched ais alarm indication is masked from providing a hardware interrupt. 5 moof out of frame alarm indication interrupt mask bit: when set to 1, the latched out of frame alarm indication is masked from providing a hardware interrupt. 4mrai rai (yellow) alarm indication interrupt mask bit: when set to 1, the latched rai (yellow) alarm indication is masked from providing a hardware interrupt. 3mcfa change in frame alignment indication interrupt mask bit: when set to 1, the latched change in frame alarm indication is masked from providing a hardware interrupt. 2moofm out of multiframe alignment (oofm) mask bit: when set to 1, detection of an out of multiframe alarm is masked from providing a hardware interrupt. 1mslip transmit or receive slip indication interrupt mask bit: when set to 1, a slip indication is masked from providing a hardware interrupt. 0 mschg signaling change of state indication interrupt mask bit: when set to 1, a change of signaling state indication is masked from providing a hardware interrupt. x+164 7 reserved: write this bit to 0. 6ais16 ts16 ais alarm indication: this bit position is used to indicate an unlatched time slot 16 ais indication. a 1 is true state. an ais in time slot 16 is detected when the received time slot has detected three or less zeros in each of two consecutive multiframe periods. recovery occurs when each of two consecutive multiframe periods contains four or more zeros or when the mul- tiframe alignment signal has been detected. 5 ecrce receive excessive crc-4 alarm error indication: a 1 indicates that 915 or more of the last 1000 crc-4 received were in error. a 0 indicates that the number of crc-4 errors was below this level. 4rai16 ts16 rai (yellow) alarm indication: this bit position is used to indicate an unlatched time slot 16 rai (yellow) alarm condition from the distant end; a 1 in bit position 6 of the time slot 16 multiframe for frame 0 indicates the alarm; three occurrences in a row will set this alarm. a 1 is a true state. 3 reserved: write this bit to 0. address (hex) bit symbol description - 251 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+164 (cont.) 2 oo16m out of ts16 multiframe alignment alarm: a 1 indicates that time slot 16 multiframe alignment has been lost. control bit eoo16m bit 1 in register x+03h enables a time slot 16 multiframe alarm. a time slot 16 multiframe alarm may be caused by two or more consecutive frame 0 of time slot 16 with the first four bits not being 0000, time slot 16 is all zeros for 16 consecu- tive frames, or basic frame alignment is lost. 1 reserved: write this bit to 0. 0auxp auxiliary pattern alarm indication: a 1 indicates that an unframed alternat- ing binary ?10? pattern has been received 254 or more times on lead rposn/rnegn or lead rnrzn for 250 microseconds. a 0 indicates either that framing has been detected or that less than 254 unframed alternating binary ?10? patterns have been detected for 250 microseconds. control bit enrxauxp must be set to a 1 for this signal to be detected. x+165 7 reserved: write this bit to 0. 6lais16 latched ts16 ais alarm indication: this bit position latches when there is a transition in the unlatched bit ais16 in register x+164h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 5 lecrce latched receive excessive crc-4 error indication: this bit position latches when there is a transition in the unlatched bit ecrce in register x+164h. this bit is set on the transition set by the rise and fall bits in reg- ister 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 4lrai16 latched ts16 rai (yellow) alarm indication: this bit position latches when there is a transition in the unlatched bit rai16 in register x+164h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the glo- bal control register or corresponding global mask bit, an interrupt is gener- ated. this bit is cleared by writing a 0 into this bit position or by the one- second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 3 reserved: write this bit to 0. address (hex) bit symbol description - 252 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+165 (cont.) 2 loo16m latched out of ts16 multiframe alignment alarm: this bit position latches when there is a transition in the unlatched bit oo16m in register x+164h. this bit is set on the transition set by the rise and fall bits in reg- ister 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the global control register or corresponding global mask bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position or by the one-second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). 1 reserved: write this bit to 0. 0lauxp latched auxiliary pattern alarm indication: this bit position latches when there is a transition in the unlatched bit auxp in register x+164h. this bit is set on the transition set by the rise and fall bits in register 00bh. a 1 is true state. if not masked by the corresponding mask bit, the gim bit in the glo- bal control register or corresponding global mask bit, an interrupt is gener- ated. this bit is cleared by writing a 0 into this bit position or by the one- second pulse, if the shadow register feature is enabled (global control bit srgen set to a 1). x+166 7 reserved: write this bit to 0. 6mais16 ts16 ais alarm indication interrupt mask bit: when set to 1, the latched ts16 ais alarm indication in register x+165h is masked from providing a hardware interrupt. 5mecrce receive excessive crc-4 error indication interrupt mask bit: when set to 1, the latched received excessive crc-4 error (lecrce) alarm indica- tion in register x+165h is masked from providing a hardware interrupt. 4mrai16 ts16 rai (yellow) alarm indication interrupt mask bit: when set to 1, the latched ts16 rai (yellow) alarm indication in register x+165h is masked from providing a hardware interrupt. 3 reserved: write this bit to 0. 2moo16m out of ts16 multiframe alignment (oo16m) mask bit: when set to 1, the latched out of ts16 multiframe alarm indication in register x+165h is masked from providing a hardware interrupt. 1 reserved: write this bit to 0. 0mauxp auxiliary pattern alarm indication interrupt mask bit: when set to 1, the latched auxp alarm indication in register x+165h is masked from providing a hardware interrupt. address (hex) bit symbol description - 253 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+167 7 reserved: write this bit to 0. 6 pais16 ts16 ais one-second error indication: enabled when control bit srgen bit 3 in register 00bh is a 1, otherwise this bit is held to 0. this bit is set to 1 when an ais alarm indication has been detected in the last one-second inter- val. 5 pecrce excessive crc-4 error one-second error indication: enabled when con- trol bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an excessive crc-4 error alarm indication has been detected in the last one- second interval. 4pra16 ts16 rai (yellow) alarm one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when a ts16 rai alarm indication has been detected in the last one-second interval. 3 reserved: write this bit to 0. 2poo16m out of ts16 multiframe alignment (oo16m): enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an oo16m alarm indication has been detected in the last one-second interval. 1 reserved: write this bit to 0. 0pauxp auxiliary pattern alarm: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 when an auxp alarm indication has been detected in the last one-second interval. x+168 7 reserved: write this bit to 0. 6fais16 ts16 ais persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one- second interval when an ts16 ais alarm indication is active, but did not become active in the last one-second interval. 5 fecrce excessive crc-4 error persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when an ecece alarm indication is active, but did not become active in the last one-second interval. 4frai16 ts16 rai (yellow) alarm persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when a ts16 rai (yellow) alarm indica- tion is active, but did not become active in the last one-second interval. 3 reserved: write this bit to 0. 2 foo16m out of ts16 multiframe alignment (oo16m) persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when an oo16m alarm indication has been detected in the last one-second interval. 1 reserved: write this bit to 0. address (hex) bit symbol description - 254 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers non-interrupt status registers these registers are read only except register x+19h which is a read to clear register. the status indications are not latched (except x+19h) and do not generate interrupts. x+168 (cont.) 0fauxp auxiliary pattern alarm persistent one-second error indication: enabled when control bit srgen is a 1, otherwise this bit is held to 0. this bit is set to 1 for a one-second interval when an auxp alarm indication is active, but did not become active in the last one-second interval. address (hex) bit symbol description x+17 7-6 reserved: write these bits to 0. 5tabit transmit a-bits indication: enabled for the transmission interface only. a 1 indicates that the transmit signaling highway a-bits are set to 1 (external ais indication). 4tybit transmit y-bit indication: enabled for the transmission interface only. a 1 indicates that the transmit signaling highway rai, r-bit (bit 3 of time slot 0 odd frames on lead ttsign) is set to 1 (external rai indication). 3-2 reserved: write these bits to 0. 1rxsf receive signaling freeze indication: a 1 indicates that the receive signal- ing bits in the signaling buffer are frozen due to loss of signal, out of frame, or the rxsfz (bit 1) in register x+134h is a 1. 0txsf transmit signaling freeze indication: a 1 indicates that the transmit sig- naling bits in the signaling buffer are frozen due to the a-bits in the signaling highway for the transmission interface are 1, or the txsfz (bit 0) in register x+134h is a 1. x+18 7 ncrc4 non-crc-4 interworking: a 1 indicates that a crc-4 to non-crc-4 inter- working has been established. when 0, this bit indicates that a crc-4 inter- working has been established. the status of this bit should be disregarded when control bit crca is 0. 6-5 reserved: indeterminate value. 4ts16me time slot 16 multiframe error. a 1 indicates an error has occurred in the time slot 16 multiframe pattern (bits 1 - 4 normally equal to 0000). this alarm will persist for one time slot multiframe period. this bit is set to a 0 if the channel is out of time slot 16 multiframe (status bit oo16m set to a 1). 3-0 reserved: indeterminate value. x+19 7-0 sigact7- sigact0 signaling activity: this read to clear register holds signaling change status indicators. each bit covers four channels. for example, sigact0 is set to a 1, if a signaling change of state has been detected for telephone channels 1, 2, 16 or 17. sigact1 covers channels 3, 4, 18 and 19. sigact7 covers chan- nels 29 and 30 only. address (hex) bit symbol description - 255 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers transmit sa4 - sa8 code registers the contents of these read/write registers may be sent in crc-4 mode for the national bits. x+175 7-6 reserved: write these bits to 0. 5s6x sa6 unknown code: a 1 indicates that the sa6 code debounced for three sub multiframes is a code that does not correspond to any other code in this register. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. 4s6f sa6 f code: a 1 indicates that the sa6 code debounced for three sub multi- frames is a 1111 code. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. 3s6e sa6 e code: a 1 indicates that the sa6 code debounced for three sub multi- frames is a 1110 code. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. 2s6c sa6 c code: a 1 indicates that the sa6 code debounced for three sub multi- frames is a 1100 code. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. 1s6a sa6 a code: a 1 indicates that the sa6 code debounced for three sub multi- frames is a 1010 code. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. 0s68 sa6 8 code: a 1 indicates that the sa6 code debounced for three sub multi- frames is a 1000 code. control bit enrxnbr (bit 3) in register x+03h must be set to a 1. address (hex) bit symbol description x+169 7-0 xsa47- xsa40 transmit sa4 byte: this register contains the sa4 byte to be transmitted for the case where control bit tsa4s (bit 4) in register x+e3h is set to a 0 and control bit sa4 (bit 4) in register x+0ch is set to a 0. bit number 7 is transmit- ted in frame 2 of the multiframe and bit 0 is transmitted in frame 16 of the mul- tiframe. x+16a 7-0 xsa57- xsa50 transmit sa5 byte: this register contains the sa5 byte to be transmitted for the case where control bit tsa5s (bit 3) in register x+e3h is set to a 0 and control bit sa5 (bit 3) in register x+0ch is set to a 0. bit number 7 is transmit- ted in frame 2 of the multiframe and bit 0 is transmitted in frame 16 of the mul- tiframe. x+16b 7-0 xsa67- xsa60 transmit sa6 byte: this register contains the sa6 byte to be transmitted for the case where control bit tsa6s (bit 2) in register x+e3h is set to a 0 and control bit sa6 (bit 2) in register x+0ch is set to a 0. bit number 7 is transmit- ted in frame 2 of the multiframe and bit 0 is transmitted in frame 16 of the mul- tiframe. address (hex) bit symbol description - 256 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers receive sa4 - sa8 code registers these read only registers contain the most recently received 8 bits for each national bit synchronized to the time slot 0 multiframe. control bit enrxnbr (bit 3) in register x+03h must be set to a 1 for data to be loaded into these registers. x+16c 7-0 xsa77- xsa70 transmit sa7 byte: this register contains the sa7 byte to be transmitted for the case where control bit tsa7s (bit 1) in register x+e3h is set to a 0 and control bit sa7 (bit 1) in register x+0ch is set to a 0. bit number 7 is transmit- ted in frame 2 of the multiframe and bit 0 is transmitted in frame 16 of the mul- tiframe. x+16d 7-0 xsa87- xsa80 transmit sa8 byte: this register contains the sa8 byte to be transmitted for the case where control bit tsa8s (bit 0) in register x+e3h is set to a 0 and control bit sa8 (bit 0) in register x+0ch is set to a 0. bit number 7 is transmit- ted in frame 2 of the multiframe and bit 0 is transmitted in frame 16 of the mul- tiframe. address (hex) bit symbol description x+16f 7-0 rsa47- rsa40 receive sa4 byte: this register contains the sa4 byte received for the case where control bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0 or 11 (crc-4 operating modes). bit number 7 is received in frame 2 of the multiframe and bit 0 is received in frame 16 of the multiframe. x+170 7-0 rsa57- rsa50 receive sa5 byte: this register contains the sa5 byte received for the case where control bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0 or 11 (crc-4 operating modes). bit number 7 is received in frame 2 of the multiframe and bit 0 is received in frame 16 of the multiframe. x+171 7-0 rsa67- rsa60 receive sa6 byte: this register contains the sa6 byte received for the case where control bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0 or 11 (crc-4 operating modes). bit number 7 is received in frame 2 of the multiframe and bit 0 is received in frame 16 of the multiframe. sa6 has additional processing functions associated with it; see registers x+175h for sa6 code detectors and registers x+177h through x+17eh for sa6 error code counters. x+172 7-0 rsa77- rsa70 receive sa7 byte: this register contains the sa7 byte received for the case where control bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0 or 11 (crc-4 operating modes). bit number 7 is received in frame 2 of the multiframe and bit 0 is received in frame 16 of the multiframe. x+173 7-0 rsa87- rsa80 receive sa8 byte: this register contains the sa8 byte received for the case where control bits crcmd1 and crcmd0 (bits 3 and 2) in register x+07h are set to x0 or 11 (crc-4 operating modes). bit number 7 is received in frame 2 of the multiframe and bit 0 is received in frame 16 of the multiframe. address (hex) bit symbol description - 257 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers performance counters and counter shadow registers the e1fx8 provides performance counter and counter shadow read/write registers for e-bit errors, crc-4 bit errors, coding violations, framing bit errors, sa6 bit errors and out of lock indications from the prbs analyzer. the counter shadow registers provide the microprocessor with an error count for the previous one-second interval. a counter and the corresponding counter shadow register (and their overflow bits) are cleared when the microprocessor writes 0 to their bits. the rising edges of a one-second interval pulse also clears the counters (and the overflow bits, if set). the shadow registers for the various counters are also updated at one-second intervals by the selected one-second clock (see control bits s1sextb, s1sint and s1ync2-s1ync0). please note that when reading unlatched counters of greater than 8 bits, the counters must be read in two consecutive read operations with the even numbered register read first. address (hex) bit symbol description x+f0 7-0 lcrc7-lcrc0 latched crc-4 error counter shadow register: this register con- tains the lower 8 bits of the 10-bit shadow register assigned for holding the crc-4 error count that occurred in the previous one-second inter- val. this location is updated from crc7-crc0 with a new count at one- second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. x+f1 7 lcrco latched crc-4 error counter overflow bit: this bit contains the overflow indication associated with the 10-bit shadow register lcrc9- lcrc0 assigned for holding the crc-4 error count that occurred in the previous one-second interval. this location is updated from crco at one-second intervals on the rising edges of the one-second clock if con- trol bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 lcrc9-lcrc8 latched crc-4 error counter shadow register: this register con- tains the upper two bits of the 10-bit shadow register assigned for hold- ing the crc-4 error count that occurred in the previous one-second interval. this location is updated from crc9-crc8 with a new count at one-second intervals on the rising edges of the one-second clock if con- trol bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+f2 7-0 crc7-crc0 crc-4 error counter: this register contains the lower 8 bits of the 10-bit crc-4 error counter. this location is cleared at one-second inter- vals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. x+f3 7 crco crc-4 error counter overflow bit: this bit contains the overflow indi- cation associated with the 10-bit crc-4 counter crc9-crc0. this bit sets when the 10-bit counter overflows. it will remain set until the micro- processor writes a 0 into this location. this location is also cleared at one-second intervals on the rising edges of the one-second clock if con- trol bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 crc9-crc8 crc-4 error counter: this register contains the upper 2 bits of the 10-bit crc-4 error counter. this location is cleared at one-second inter- vals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. - 258 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+f4 7-0 lcv7-lcv0 latched coding violation error counter shadow register: this reg- ister contains the lower 8 bits of the 16-bit shadow register assigned for holding the hdb3 coding violation count that occurred in the previous one-second interval. this location is updated from cv7-cv0 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 16-bit count. x+f5 7-0 lcv15-lcv8 latched coding violation error counter shadow register: this reg- ister contains the upper 8 bits of the 16-bit shadow register assigned for holding the hdb3 coding violation count that occurred in the previous one-second interval. this location is updated from cv15-cv8 with a new count at one-second intervals on the rising edges of the one-sec- ond clock if control bit srgen is set to a 1. bit 7 is the msb of the 16-bit count. x+f6 7 lcvo latched coding violation error counter overflow bit: this bit con- tains the overflow indication associated with the 16-bit shadow register lcv15-lcv0 assigned for holding the coding violation count that occurred in the previous one-second interval. this location is updated from cvo at one-second intervals on the rising edges of the one-sec- ond clock if control bit srgen is set to a 1. 6-0 reserved: write these bits to 0. x+f7 7-0 cv7-cv0 coding violation counter: this register contains the lower 8 bits of the 16-bit hdb3 coding violation counter. this location is cleared at one- second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 16-bit count. x+f8 7-0 cv15-cv8 coding violation counter: this register contains the upper 8 bits of the 16-bit hdb3 coding violation counter. this location is cleared at one- second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 7 is the msb of the 16-bit count. x+f9 7 cvo coding violation counter overflow bit: this bit contains the overflow indication associated with the 16-bit coding violation counter cv15- cv0. this bit sets when the 16-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-0 reserved: write these bits to 0. x+fa 7-0 lfbe7-lfbe0 latched framing word error counter shadow register: this regis- ter contains 8 bit shadow register assigned for holding the framing word errors that occurred in the previous one-second interval. this location is updated from fbe7-fbe0 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. this counter may be used to determine ber thresholds for itu-t g.732. address (hex) bit symbol description - 259 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+fb 7 lfbeo latched framing bit error counter overflow bit: this bit contains the overflow indication associated with the 8-bit shadow register lfbe7- lfbe0 assigned for holding the framing word error count that occurred in the previous one-second interval. this location is updated from fbeo at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-0 reserved: write these bits to 0. x+fc 7-0 fbe7-fbe0 framing word error counter: this register contains the 8 bit framing word error counter. a framing word error is counted as either an incor- rect fas pattern in time slot 0 (fas frames) or bit 2 of time slot 0 (nfas frames) not being a 1. this location is cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. x+fd 7 fbeo framing bit error counter overflow bit: this bit contains the over- flow indication associated with the 8-bit framing bit error counter fbe7- fbe0. this bit sets when the 8-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-0 reserved: write these bits to 0. x+fe 7-0 lebe7-lebe0 latched e-bit error counter shadow register: this register contains the lower 8 bits of the 10-bit shadow register assigned for holding the e-bit error count that occurred in the previous one-second interval. this location is updated from ebe7-ebe0 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. x+ff 7 lebeo latched e-bit error counter overflow bit: this bit contains the overflow indication associated with the 10-bit shadow register lebe9- lebe0 assigned for holding the e-bit error count that occurred in the previous one-second interval. this location is updated from ebeo at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 lebe9-lebe8 latched e-bit error counter shadow register: this register contains the upper two bits of the 10-bit shadow register assigned for holding the e-bit error count that occurred in the previous one-second interval. this location is updated from ebe9-ebe8 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+100 7-0 ebe7-ebe0 e-bit error counter: this register contains the lower 8 bits of the 10-bit e-bit error counter; when the e1fx8 framer is in multiframe alignment, each e-bit received as a 0 is counted in this counter. this location is cleared at one-second intervals between the rising and falling edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. address (hex) bit symbol description - 260 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+101 7 ebeo e-bit error counter overflow bit: this bit contains the overflow indi- cation associated with the 10-bit e-bit counter ebe9-ebe0. this bit sets when the 10-bit counter overflows. it will remain set until the micropro- cessor writes a 0 into this location. this location is also cleared at one- second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 ebe9-ebe8 e-bit error counter: this register contains the upper 2 bits of the 10-bit e-bit error counter; when the e1fx8 framer is in multiframe alignment, each e-bit received as a 0 is counted in this counter. this location is cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+157 7-0 ltestp7- lt e s t p 0 latched time slot test pattern out of lock counter shadow reg- ister: this register holds the lower 8 bits of the 15 bit register used for the out of lock indications. x+158 7 ltstpo latched time slot test pattern out of lock counter overflow bit shadow register: this register holds the overflow bit of the 15 bit reg- ister used for the out of lock indications. 6-0 ltestp14- lt e s t p 8 latched time slot test pattern out of lock counter shadow reg- ister: this register holds the upper 7 bits of the 15 bit register used for the out of lock indications. x+159 7-0 testp7- testp0 time slot test pattern out of lock counter: this register holds the lower 8 bits of the 15 bit register used for the out of lock indications from the prbs/ code word analyzer. x+15a 7 testpo time slot test pattern out of lock counter overflow bit: this reg- ister holds the overflow bit of the 15 bit register used for the out of lock indications. 6-0 testp14- testp8 time slot test pattern out of lock counter: this register holds the upper 7 bits of the 15 bit register used for the out of lock indications from the prbs/ code word analyzer. x+177 7-0 lsa617- lsa610 latched sa6-bit error counter #1 shadow register: this register contains the lower 8 bits of the 10-bit shadow register assigned for hold- ing the sa6-bit error count that occurred in the previous one-second interval. this location is updated from sa617-sa610 in register x+179h with a new count at one-second intervals on the rising edges of the one- second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. address (hex) bit symbol description - 261 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+178 7 lsa61o latched sa6-bit error counter #1 overflow bit: this bit contains the overflow indication associated with the 10-bit shadow register lsa619- lsa610 assigned for holding the sa6 error count that occurred in the previous one-second interval. this location is updated from sa61o at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 lsa619- lsa618 latched sa6-bit error counter #1 shadow register: this register contains the upper two bits of the 10-bit shadow register assigned for holding the sa6-bit error count that occurred in the previous one-second interval. this location is updated from sa619 and sa618 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+179 7-0 sa617-sa610 sa6-bit error counter #1: this register contains the lower 8 bits of the 10-bit sa6 error counter that counts alarms from terminal equipment; sa6 codes of 0001 or 0011 in every received sub multiframe are counted in this counter if control bit enrxnbr is set to a 1. this loca- tion is cleared at one-second intervals between the rising and falling edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. x+17a 7 sa61o sa6-bit error counter #1 overflow bit: this bit contains the overflow indication associated with the 10-bit sa6 bit error counter sa619- sa610. this bit sets when the 10-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 sa619-sa618 sa6-bit error counter #1: this register contains the upper 2 bits of the 10-bit sa6 error counter that counts alarms from terminal equipment; sa6 codes of 0001 or 0011 in every received sub multiframe are counted in this counter if control bit enrxnbr is set to a 1. this loca- tion is cleared at one-second intervals on the rising edges of the one- second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+17b 7-0 lsa627- lsa620 latched sa6-bit error counter #2 shadow register: this register contains the lower 8 bits of the 10-bit shadow register assigned for hold- ing the sa6-bit error count that occurred in the previous one-second interval. this location is updated from sa627 - sa620 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. address (hex) bit symbol description - 262 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+17c 7 lsa62o latched sa6-bit error counter #2 overflow bit: this bit contains the overflow indication associated with the 10-bit shadow register lsa629- lsa620 assigned for holding the sa6 error count that occurred in the previous one-second interval. this location is updated from sa62o at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 lsa629- lsa628 latched sa6-bit error counter #2 shadow register: this register contains the upper two bits of the 10-bit shadow register assigned for holding the sa6-bit error count that occurred in the previous one-second interval. this location is updated from sa629 and sa628 with a new count at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. x+17d 7-0 sa627-sa620 sa6-bit error counter #2: this register contains the lower 8 bits of the 10-bit sa6 error counter that counts alarms from the t reference point; sa6 codes of 0010 or 0011 in every received sub multiframe are counted in this counter if control bit enrxnbr is set to a 1. this loca- tion is cleared at one-second intervals between the rising and falling edges of the one-second clock if control bit srgen is set to a 1. bit 0 is the lsb of the 10-bit count. x+17e 7 sa62o sa6-bit error counter #2 overflow bit: this bit contains the overflow indication associated with the 10-bit sa6 bit error counter sa629- sa620. this bit sets when the 10-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one-second intervals on the rising edges of the one-second clock if control bit srgen is set to a 1. 6-2 reserved: write these bits to 0. 1-0 sa629-sa628 sa6-bit error counter #2: this register contains the upper 2 bits of the 10-bit sa6 error counter that counts alarms from the t reference point; sa6 codes of 0010 or 0011 in every received sub multiframe are counted in this counter if control bit enrxnbr is set to a 1. this loca- tion is cleared at one-second intervals on the rising edges of the one- second clock if control bit srgen is set to a 1. bit 1 is the msb of the 10-bit count. address (hex) bit symbol description - 263 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers test generation registers these read/write registers control error insertion, prbs generator/analyzer at the e1 level and loopback at the e1 level. address (hex) bit symbol description x+106 7 crce generate a crc-4 error: this feature is enabled when control bits crcmd1 and crcmd0 are equal to x0, or 11 (i.e., this enables the crc-4 feature). when crce is set to 1, the crc-4 bits in time slot 0 are transmitted in the inverted state once. to send another crc-4 error, this bit must be first written with a 0, and then a 1. 6frme transmit framing error: when set to a 1, a single fas framing word includ- ing the international bit is transmitted inverted for one frame. the microproces- sor must write a 0 into this bit position before another framing error can be transmitted. 5bpve transmit bipolar violation error: when the rail interface is selected, a 1 causes a single bpv error to be sent. the microprocessor must write a 0 into this bit position before another bpv error can be transmitted. 4nfase transmit nfas error: when set to a 1, bit 2 in time slot 0 for a non frame alignment frame (nfas) is sent as a 0 for a single frame. the microprocessor must write a 0 into this bit position before another nfas framing error can be transmitted. 3-2 reserved: write these bits to 0. 1prbre prbs receiver enable: when this bit is set to 1, the internal prbs analyzer is enabled for analyzing a prbs pattern present at the output of the ami/ hdb3 decoder. control bits tprn2- 0 (bits 4-2) in register x+109h determine the pattern expected and control bit rtfm (bit 7) in register x+01h when set to 1 enables the prbs analyzer to search over all of the bits including time slot 0. if rtfm is set to a 0, time slot 0 is considered as don?t care. the prbs analyzer provides an output to status bit tplol (bit 5) in register x+129h as well as counter testp0-testp14 in registers x+159h and x+15ah. control bit sprbre (bit 1) in register x+107h must be set to a 0. 0 inprbs insert prbs: when set to 1, prbs is inserted in place of the data from the transmit data highway. control bit ttfm (bit 6) in register x+01h when set to a 0 causes time slot 0 to overwrite the pattern. control bit sinsprbs (bit 0) in register x+107h must be set to a 0. - 264 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+107 7 llp local loopback enable: a 1 enables the loopback feature. transmit data, after the codec is looped back as received data. when control bit txlais is a 1, ais is transmitted in place of test data. 6txlais transmit ais in local loopback: when set to a 1, ais is transmitted on the line only while local loopback is enabled (control bit llp is set to a 1) when set to a 0 the signal being looped back is also sent to the line. 5rlp remote line loopback enable: a 1 enables the remote line loopback fea- ture. receive line data prior to the codec but after the dejitter buffer is looped back as the transmit line data. when both llp and rlp are set to a 1, a bidi- rectional loopback is enabled; the dejitter buffer is not included in the bidirec- tional loopback (where x=don?t care). 4plp payload loopback enable: a 1 enables the payload loopback feature. the receive system data stream is looped back as the transmit data stream. the transmit framing pattern is not overwritten by the received signal. the relation- ship between a received time slot and the received time slot 0 is not main- tained (either time slot number or bit position) when the payload is looped back. 3-2 reserved: write these bits to 0. 1sprbre system side prbs receiver enable: when this bit is set to 1, the internal prbs analyzer is enabled for analyzing a prbs pattern present at the input of the transmit slip buffer. control bits tprn2- 0 (bits 4-2) in register x+109h determine the pattern expected. the prbs analyzer provides an output to status bit tplol (bit 5) in register x+129h as well as counter testp0 -14 in registers x+159h and x+15ah. control bit prbre (bit 1) in register x+106h must be set to a 0. 0 sinprbs system side prbs insertion: when set to 1, prbs is inserted in place of the data to the receive data highway. control bit insprbs (bit 0) in register x+106h must be set to a 0. address (hex) bit symbol description bypass llp rlp loopback 0 0 0 none without dejitter buffer in rx path 1 0 0 none with dejitter buffer in rx path x 1 0 local without dejitter buffer 0 0 1 remote without dejitter buffer in rx path 1 0 1 remote with dejitter buffer in rx path x 1 1 bi-directional without dejitter buffer - 265 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot/ds0 loopback, test pattern status and dpll status registers these registers provide the status and control for the ds0 loopback activate and deactivate sequences as well as providing the n x ds0 prbs and dpll status. register x+129h is read-only, the rest are read/write. address (hex) bit symbol description x+129 7 ds0act ds0 receive remote loopback activation request: an unlatched indi- cation that indicates that the ds0 receive remote loopback activation request has been received on the time slots defined by control bits tsll32- tsll1 in registers x+12dh, x+12eh, x+12fh and x+130h when control bit tsrlop (bit 7 in register x+109h) is set to a 0 and control bit rlpen (bit 0 in register x+109h) is set to a 1. the activation request signal is a 2 7 - 1 prbs pattern applied for 2 seconds followed by 2 seconds of all ones as defined in ansi t1.403-1998. 6 ds0dct ds0 receive remote loopback deactivation request: an unlatched indication that indicates that the ds0 receive remote loopback deactivation request has been received on the time slots defined by control bits tsll32- tsll1 in registers x+12dh, x+12eh, x+12fh and x+130h when control bit tsrlop (bit 7 in register x+109h) is set to a 0 and control bit rlpen (bit 0 in register x+109h) is set to a 1. the deactivation request signal is a 2 7 -1 prbs pattern inverted applied for 2 seconds followed by 2 seconds of all ones as defined in ansi t1.403-1998. 5tplol receive out of lock indication: an unlatched indication that indicates that the time slot or e1 prbs test pattern out of lock occurred or a mis- match has occurred against the microprocessor written ds0 code word value. for this indication to be valid, the received signal and analyzer must be in the same mode (framed or unframed). the status of the out of lock indication for the prbs analyzer is checked on a bit-by-bit basis when set for a prbs pattern. a code word is checked on a byte-by-byte basis and is assumed to be contiguous. control bits tprn2, tprn1 and tprn0 (bits 4, 3 and 2 in register x+109h) determine the pattern to be detected. for code words, the pattern is held in registers x+15bh through x+15eh; control bits rtpae or srtpae (bit 2 and 0 in register x+131h) must be set to a 1 to enable the analyzer for nx time slot analysis, while control bit prbre or sprbre (bits 1 in registers x+106h or x+107h) must be set to a 1 for e1 analysis. 4ds0txc ds0 transmit remote loopback activation or deactivation request completed: an unlatched indication that indicates that the ds0 transmit remote loopback activation/deactivation request of four-second duration has been completely transmitted. control bit trdslp (bit 5 in register x+109h) is set to 1 to send the entire sequence of 2 seconds of the prbs pattern fol- lowed by 2 seconds of all ones on the time slots selected by tsrl32- tsrl1 in registers x+10dh, x+10ch, x+10bh and x+10ah and enabled by tsrlop (bit 7 in register x+109h) set to a 1. control bit ds0da (bit 6 in register x+109h) set to 0 selects an activation request or set to 1 selects a deactivation request. - 266 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+129 (cont.) 3intact intermediate indication for ds0 receive remote loopback activate request: a 1 in this bit position indicates that the ds0 loopback code acti- vate prbs pattern (2 7 -1) has been detected for n frames where control bits srtt7-srtt0 in register x+12ch determine the value n and when the fraction being monitored is determined by control bits tsll32-tsll1 in reg- isters x+130h, x+12fh, x+12eh, and x+12dh. control bit tsrlop (bit 7 in register x+109h) must be set to a 0 and control bit rlpen (bit 0 in regis- ter x+109h) must be set to a 1 for detection to take place. 2 intdct intermediate indication for ds0 receive remote loopback deactivate request: a 1 in this bit position indicates that the ds0 loopback code deac- tivate prbs pattern (2 7 -1 inverted) has been detected for n frames where control bits srtt7- srtt0 in register x+12ch determine the value n and when the fraction being monitored is determined by control bits tsll32- tsll1 in registers x+130h, x+12fh, x+12eh, and x+12dh. control bit tsrlop (bit 7 in register x+109h) must be set to a 0 and control bit rlpen (bit 0 in register x+109h) must be set to a 1 for detection to take place. 1overf dpll fifo overflow indication: this bit position indicates when a specific framer has detected a dpll fifo overflow. this bit position is cleared when the corresponding framer indication is cleared 0 underf dpll fifo underflow indication: this bit position indicates when a specific framer has detected a dpll fifo underflow. this bit position is cleared when the corresponding framer indication is cleared x+12a 7 lds0act latched ds0 receive remote loopback activation request: a latched indication that indicates that the ds0 receive remote loopback activation request was received. this bit is set only on the positive transition of status bit ds0act (bit 7) in register x+129. 6 lds0dct latched ds0 receive remote loopback deactivation request: a latched indication that indicates that the ds0 receive remote loopback deac- tivation request was received. this bit is set only on the positive transition of status bit ds0dct (bit 6) in register x+129. 5ltplol latched receive out of lock indication. a latched indication that indi- cates that the time slot or e1 prbs test pattern out of lock occurred or a mismatch has occurred against the microprocessor written code word value. this bit is set only on the positive transition of status bit tplol (bit 5) in reg- ister x+129. 4lds0txc latched ds0 transmit remote loopback activation or deactivation request completed: a latched indication that indicates that the ds0 trans- mit remote loopback activation/deactivation request has been transmitted. this bit is set only on the positive transition of status bit ds0txc (bit 4) in register x+129. 3lintact latched intermediate indication for ds0 receive remote loopback activate request: a latched indication that indicates that the intermediate ds0 receive remote loopback activate prbs pattern has been received. this bit is set only on the positive transition of status bit intact (bit 3) in register x+129. address (hex) bit symbol description - 267 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+12a (cont.) 2 lintdct latched intermediate indication for ds0 receive remote loopback deactivate request: a latched indication that indicates that the intermedi- ate ds0 receive remote loopback deactivate prbs pattern has been received. this bit is set only on the positive transition of status bit intdct (bit 2) in register x+129. 1loverf latched dpll fifo overflow indication: this bit position latches when there is a transition in the unlatched bit overf in register x+129h. a 1 is true state. if not masked by the corresponding mask bit or the gim bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. this bit is set only on the positive transition of status bit overf (bit 1) in register x+129. 0 lunderf latched dpll fifo underflow indication: this bit position latches when there is a transition in the unlatched bit underf in register x+129h. a 1 is true state. if not masked by the corresponding mask bit or the gim bit, an interrupt is generated. this bit is cleared by writing a 0 into this bit posi- tion.this bit is set only on the positive transition of status bit underf (bit 0) in register x+129. x+12b 7 mdact mask ds0 receive remote loopback activation request indication: a 1 will mask a remote loopback activation request from generating an inter- rupt indication. 6 mddct mask ds0 receive remote loopback deactivation request indication: a 1 will mask a remote loopback deactivation request from generating an interrupt indication. 5mtplol mask receive out of lock indication: a 1 will mask a ds0 test pattern out of lock from generating an interrupt indication. 4mds0txc mask ds0 transmit remote loopback activation/ deactivation request completed indication: a 1 will mask the transmit remote loop- back activation/deactivation request completed indication from generating an interrupt indication. 3mintact mask intermediate indication for ds0 receive remote loopback acti- vate request: a 1 will mask a remote loopback activate prbs pattern from generating an interrupt indication. 2mintdct mask intermediate indication for ds0 receive remote loopback deac- tivate request: a 1 will mask a remote loopback deactivate prbs pattern from generating an interrupt indication. 1moverf mask dpll fifo overflow indication: a 1 will mask a dpll fifo over- flow from generating an interrupt indication. 0 munderf mask dpll fifo underflow indication: a 1 will mask a dpll fifo underflow from generating an interrupt indication. address (hex) bit symbol description - 268 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers time slot/ds0 test pattern control registers these registers provide the status and control for the ds0 loopback activate and deactivate sequences as well as providing the n x time slot controls and prbs controls. these registers are read/write. address (hex) bit symbol description x+109 7 tsrlop time slot remote loopback enable: a 1 enables the ansi remote ds0 loopback feature, and also enables the time slot mode in the prbs generator. the local loopback control bits are now used for sending the remote loopback sequence for the designated time slots. a 0 enables a remote time slot loop- back as determined by control bits tsrl32-tsrl1 in registers x+10ah through x+10dh. 6ds0da ds0 remote loopback activation request: a 1 sets the ds0 remote loop- back sequence generator for transmitting the four-second long ds0 remote loopback deactivation request. a 0 sets the ds0 remote loopback sequence generator for transmitting the four-second long ds0 remote loopback activa- tion request. see ansi t1.403-1998 for the specific pattern. 5trdslp transmit ds0 remote loopback activation or deactivation request: a 1 written to this bit position causes a ds0 deactivation sequence to be transmitted when control bit ds0da in this register is a 1 or an activation sequence to be transmitted when control bit ds0da is a 0. the ds0 channel in which the sequence is to be transmitted is determined by control bits tsrl32-tsrl1in registers x+10ah through x+10dh. to send another sequence this bit must be first written with a 0, followed by a 1. 4-2 tprn2- tprn0 time slot test pattern selection: the time slot test pattern is selected according to the following table (where x=don?t care). tprn2 tprn1 tprn0 action x 0 0 not used 0 0 1 2 20 -1 (qrss) 0 1 0 2 15 -1 1 0 1 2 11 -1 1 1 0 2 23 -1 x 1 1 register test word 1tsllp time slot local loopback enable: a 1 enables the time slot local loopback feature and the time slots selected for local loopback are determined by con- trol bits tsll32-tsll1. 0 rlpen receive ds0 remote loopback detection enabled: a 1 enables the ds0 remote loopback detector for detecting the activate and deactivate sequence. x+10a 7-0 tsrl8- tsrl1 time slot 7 to 0 remote loopback control: a 1 written to one or more con- trol bits in this register causes the designated time slots to be remotely looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e4h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. for framing enabled (ttfm control bit in register x+01h not equal to 1), time slot 0 is not looped back. - 269 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+10b 7-0 tsrl16- tsrl9 time slot 15 to 8 remote loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be remotely looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e5h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. for signaling enabled (typ1, typ0 control bits in register x+134h not equal to 00), time slot 16 is not looped back. x+10c 7-0 tsrl24- tsrl17 time slot 23 to 16 remote loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be remotely looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e6h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. x+10d 7-0 tsrl32- tsrl25 time slot 31 to 24 remote loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be remotely looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e7h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. x+12c 7 - 0 srtt7- srtt0 select frame count for receive activation and deactivation indication: the value written into this register determines the number of frames after lock is acquired before the activation or deactivation indication is acceptable. value must be non zero. x+12d 7-0 tsll8- tsll1 time slot 7 to 0 local loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be locally looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e4h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. x+12e 7-0 tsll16- tsll9 time slot 15 to 8 local loopback control: a 1 written to one or more con- trol bits in this register causes the designated time slots to be locally looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e5h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. x+12f 7-0 tsll24- tsll17 time slot 23 to 16 local loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be locally looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e6h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. x+130 7-0 tsll32- tsll25 time slot 31 to 24 local loopback control: a 1 written to one or more control bits in this register causes the designated time slots to be locally looped back, transmitted with the payload, or a selected test pattern. control bit tden in register x+e7h corresponding to the time slot to be looped back must be set to a 1 even if control bit txsbe (bit 5) in register x+11ch is set to a 0. address (hex) bit symbol description - 270 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers x+131 7-4 reserved: write these bits to 0. 3sprn send time slot test pattern: a 1 sends the test pattern selected by control bits tprn2, tprn1 and tprn0, for the time slots selected by control bits tsrln. 2rtpae receive test pattern detector enabled: a 1 enables the time slot test pat- tern detector. the time slots analyzed are selected by control bits tsll32- tsll1 in registers x+12dh through x+130h and the pattern searched for is selected by control bits tprn2 - tprn0 in this register. the out of lock indi- cation is given in status bit tplol (bit 5 in register x+129h) with a latched value in bit ltplol (bit 5 in register x+12ah). out of locks are counted as testp14 - testp0 with overflow bit testpo in registers x+159h and x+15ah. shadow registers ltest14 - ltest0 with overflow bit ltesto are provided in x+157h and x+158h. 1ssprn send system side time slot test pattern: a 1 sends the test pattern selected by control bits tprn2, tprn1 and tprn0, for the channels selected by control bits tslln. 0srtpae system side receive test pattern detector enabled: a 1 enables the time slot test pattern detector. the time slots analyzed are selected by control bits tsrl32- tsrl1 in registers x+10ah through x+10dh and the pattern searched for is selected by control bits tprn2-tprn0 in this register. the out of lock indication is given in status bit tplol (bit 5 in register x+129h) with a latched value in bit ltplol (bit 5 in register x+12ah). out of locks are counted as testp14-testp0 with overflow bit testpo in registers x+159h and x+15ah. shadow registers ltest14-ltest0 with overflow bit ltesto are provided in x+157h and x+158h. x+15b 7-0 test word byte 1 time slot test word register byte 1: this register is used for sending a microprocessor test pattern when control bits tprn1 and tprn0 are equal to 11. this word is transmitted first. bit 7 is transmitted first. x+15c 7-0 test word byte 2 time slot test word register byte 2: this register is used for sending a microprocessor test pattern when control bits tprn1 and tprn0 are equal to 11. this word is transmitted second. bit 7 is transmitted first. x+15d 7-0 test word byte 3 time slot test word register byte 3: this register is used for sending a microprocessor test pattern when control bits tprn1 and tprn0 are equal to 11. this word is transmitted third. bit 7 is transmitted first. x+15e 7-0 test word byte 4 time slot test word register byte 4: this register is used for sending a microprocessor test pattern when control bits tprn1 and tprn0 are equal to 11. this word is transmitted forth. bit 7 is transmitted first. address (hex) bit symbol description - 271 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers test registers address (hex) bit symbol description x+1ff 7-3 reserved: write these bits to 0. 2oblol observe out of lock: this bit is for testing purposes and must be set to 0 for normal operation. when set to 1, status bit tplol is substituted for the normal signal on lead rtauxn. with a high indicating out of lock. 1rxfs receive fast sync enable: this bit used for testing purposes and for exter- nally synchronizing the framer. it must be a 0 for normal framing detection. if control bit rail (bit 7 in register x+00h) is set to 0, control bit exlos (bit 3 in register x+00h) is set to a 1, and this bit is set to a 1, a positive, single rclkn clock cycle wide pulse on lead rscann will force the framer to inter- pret the next bit as the first bit of a multiframe. 0 reserved: write this bit to 0. - 272 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers application diagrams the e1fx8 can be used in a wide range of telecommunication and data communication applications: internet access equipment with e1 and fractional e1 ports dcs, digital central office or remote digital terminals (exchange terminations and access nodes) sdh terminal or add/drop multiplexers supporting e1 byte-synchronous operation or e1monitoring with g.706 annex c the following diagram illustrates typical applications using the e1fx8. figure 66. typical applications using the e1fx8 the application diagram in figure 66 shows four different uses for the e1fx8. for a frame relay application the e1fx8 is connected to a multi-channel hdlc controller. the e1fx8 is also shown above being used as an sdh/stm-1 add/drop async multiplexer application, quad fractional e1 csu/dsu application and atm switch uni or ima application. e1fx8 TXC-03109 liu 8 rtclkx8 rtdatx8 rtfrmx8 ttclkx8 ttdatx8 ttfrmx8 multichannel hdlc controller packet proc. bposc scout1, 2 ref. clock e1 liu e1 liu e1 e1fx8 TXC-03109 cobra utopia-1 1 2 rtdatx8 rtsigx8 ttdatx8 ttsigx8 sti 0-7 sti 0-7 sto 0-7 sto 0-7 time-space switch sti 0-7 sti 0-7 sto 0-7 sto 0-7 mt8980 proc. system TXC-03109 e1fx8 crosspoint (speech) signaling crosspoint (signaling) liu liu liu 8 txc-03361 e123mux mrt txc- 02050 syn155c txc- 02302b txc-03003b sot-3 txc-04252 qe1m 16 or 21 e1s 1 2 (3) 1 6 21 e1s g.703 g.703 g.703 34 mbit/s stm-1 e1 g.703 e1 g.703 e1 g.703 e1fx8 TXC-03109 liu liu liu e1 g.703 e1 g.703 e1 g.703 e1 g.703 liu network interface liu liu liu e1 g.703 e1 g.703 e1 g.703 e1 g.703 liu terminal interface proc. system dte 1/f dte 1/f dte v.35/x.21 v.35/x.21 interfaces 16 e1s - 273 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers package information the e1fx8 device is available in two package formats. one is a 208-lead plastic ball grid array package suitable for surface mounting, as illustrated in figure 67. the other is a 256-l ead plastic ball grid array package suitable for surface mounting, as illustrated in figure 68. figure 67. e1fx8 TXC-03109 208-lead plastic ball grid array package diagram 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trpnmlkjhgfedcb b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 (a3) a a1 dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 16 x 16, jedec code mo-151-aaf-1 a a1 a2 1.35 0.30 0.75 1.75 0.50 0.85 a3 (ref.) 0.36 b 0.40 0.60 d 17.00 d1 (bsc) 15.00 d2 15.00 15.70 e 17.00 e1 (bsc) 15.00 e2 15.00 15.70 e (bsc) 1.00 bottom view transwitch TXC-03109aiog 16 a - 274 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers figure 68. e1fx8 TXC-03109 256-lead plastic ball grid array package diagram 1 y b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 (a3) a a1 dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 20 x 20, jedec code mo-151-bal-2. a a1 a2 1.92 0.50 1.12 2.32 0.70 1.22 a3 (ref.) 0.36 b 0.60 0.90 d 27.00 d1 (bsc) 24.13 d2 23.50 24.70 e 27.00 e1 (bsc) 24.13 e2 23.50 24.70 e (bsc) 1.27 bottom view transwitch TXC-03109aibg 20 a 2 3 4 5 6 7 8 10 9 11 13 12 19 18 17 16 15 14 wvut rpnmlkjhgfedcb - 275 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: TXC-03109aiog 208-lead plastic ball grid array package part number: TXC-03109aibg 256-lead plastic ball grid array package related products txc-02050, mrt multi-rate line interface device. the mrt directly interfaces with the e123mux device and provides the functions for terminating itu-t-specified 8448 kbit/s (e2) and 34368 kbit/s (e3) line rate signals, or 6312 kbit/s (jt2) line signals specified in the japanese ntt technical reference for high speed digital leased circuits. an optional hdb3 codec is provided for the two itu-t line rates. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data out- put). transmits and receives at sts-3/stm-1 rates. provides the complete sts-3/ stm-1 frame synchronization function. connects directly to optical fiber interface components. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this device performs section, line and path overhead processing for stm-1/sts-3/ sts-3c signals. compliant with ansi and itu-t standards. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). this device provides extended features relative to the 84-lead txc-03001 and txc-03001b sot-1 devices, and it has a 144-lead package. txc-03108, t1fx8 vlsi device (8-channel t1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfac- ing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-03114, qe1f- plus vlsi device (quad e1 framer- plus ). the qe1f- plus is a 4-channel e1 (2048 kbit/s) framer designed for voice and data communications appli- cations. a dual unipolar or nrz line interface is supported with full alarm detection and generation per itu-t g.703 and operates from a power supply of 3.3 or 5 volts. txc-03361, e123mux vlsi device (e1/e2/e3 mux/demux). the e123mux is a cmos vlsi device that provides the e13 functions needed to multiplex and demulti- plex 16 independent e1 signals to and from an e3 signal that conforms to the itu-t g.751 recommendation. the e123mux can also be configured to operate as an e12 or e23 multiplexer and demultiplexer. txc-04252, qe1m vlsi device (quad e1 to au-4/vt2 or tu-12 async mapper- desync). interconnects four e1 signals with any four asynchronous mode vt2 or tu-12 tributaries carried in sdh au-4/au-3 rate payload interface. txc-04216, e1mx16 vlsi device (sixteen channel e1 to au-4/vt2 or tu-12 async mapper-desync). interconnects sixteen e1 signals with any sixteen asynchronous mode vt2 or tu-12 tributaries carried in sdh au-4/au-3 rate payload interface. txc-05101c, hdlc vlsi device (hdlc controller, 36-bit terminal i/o). high speed high level data link controller that sends and receives packets at line rates up to 51.84 mbit/s using either a nibble, byte-parallel, or serial interface. txc-05150, cdb vlsi device (cell delineation block). provides cell delineation for atm cells carried in a physical line at rates of 1.544 to 155 mbit/s. - 276 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers txc-05427c, cobra vlsi device (constant bit rate atm adaptation layer 1). pro- vides atm aal1 structured and unstructured service for four t1, e1 or n x 64k con- stant bit rate interfaces. this device is not recommended for use in new designs. txc-06101, phast-1 vlsi device (sonet sts-1 overhead terminator). this device provides the same features as the txc-03011b sot-1e device in the same package with the same pin outs, except it operates from a power supply of 3.3 volts. txc-06103, phast-3n vlsi device (sonet/sdh stm-1, sts-3 or sts-3c over- head terminator) this phast-3n vlsi device provides a combus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06112, phast-12 vlsi device (sonet/sdh stm-1, stm-4 sts-12 or sts-3c section and line overhead terminator) this phast-12 vlsi device provides a combus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06125, xbert vlsi device (bit error rate generator/receiver). programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability. - 277 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: 212-642-4900 11 west 42nd street fax: 212-302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: 650-949-6700 suite 304 fax: 650-949-6705 mountain view, ca 94040 web: www.atmforum.org atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium web: www.euroinfo@atmforum.ocm atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan web: www.apinfo@atmforum.com bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: 800-854-7179 (within u.s.a.) global engineering documents tel: 314-726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: 314-726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: 800-669-6857 (within u.s.a.) tel: 903-769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: 508-650-1375 washington, dc 20007 web: www.mvip.org - 278 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: 215-697-2179 building 4 / section d fax: 215-697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: 800-433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: 503-693-6232 (outside u.s.a.) hillsboro, or 97124 fax: 503-693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: 800-521-core (within u.s.a.) attention - customer service tel: 908-699-5800 (outside u.s.a.) 8 corporate place fax: 908-336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsucho - suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo - 279 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within this updated e1fx8 data sheet that have significant differences relative to the previous and now superseded e1fx8 data sheet: updated e1fx8 data sheet: preliminary ed. 3, january 2001 previous e1fx8 data sheet: preliminary ed. 2, february 2000 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 42 deleted ?component temperature x time? row from the first table. 55 added pulse width of rtfrmn signal as symbol t pw in figure 14 diagram and table. added note 2 to table. 56 added pulse width of ttfrmn signal as symbol t pw in figure 15 diagram and table. added note 2 to table. 58 added pulse width of rtfrmn signal as symbol t pw in figure 17 diagram and table. added note 2 to table. 59 added pulse width of ttfrmn signal as symbol t pw in figure 18 diagram and table. added note 2 to table. 279 replaced list of data sheet changes. - 280 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers - notes - - 281 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. preliminary information documents contain information on products in the sampling, prepro- duction or early production phases of the product life cycle. characteristic data and other specifica- tions are subject to change. contact transwitch applications engineering for current information on this product. transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 - 283 of 284 - e1fx8 TXC-03109 preliminary TXC-03109-mb ed. 3, january 2001 data sheet proprietary transwitch corporation information for use solely by its customers documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required |
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